soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index d32d7ba64da48c0a31936099a4c856431467c8df..b79a7fd6c9e260329a8fa7a0354006dff8f6838c 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -88,6 +88,7 @@ class LM32(Module):
                 "lm32_debug.v",
                 "lm32_itlb.v",
                 "lm32_dtlb.v")
+        platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl"))
         if variant == "minimal":
             platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
         elif variant == "lite":