sim/core: fix Cat bitshift

diff --git a/migen/sim/core.py b/migen/sim/core.py
index af3f3734f97debc4bb3184c97ee78af32c9e75fb..157d63ff73a1ca73e8464d2a8f834ccff24942b3 100644 (file)
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@@ -156,10 +156,11 @@ class Evaluator:
                 value -= 2**node.nbits
             self.modifications[node] = value
         elif isinstance(node, Cat):
+            nbits = 0
             for element in node.l:
+                value >>= nbits
                 nbits = len(element)
                 self.assign(element, value & (2**nbits-1))
-                value >>= nbits
         elif isinstance(node, _Slice):
             full_value = self.eval(node.value, True)
             # clear bits assigned to by the slice