substr() -> compare()

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 5be6d60fd9672eab8907748c9c151fce18c0b20f..73b1e7d530bd7a796216cf6a576311eb26c2df0a 100644 (file)
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -363,7 +363,7 @@ struct FirrtlWorker
                                }
                                // Check for subfield assignment.
                                std::string bitsString = "bits(";
-                               if (sinkExpr.substr(0, bitsString.length()) == bitsString ) {
+                               if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) {
                                        if (sinkSig == nullptr)
                                                log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
                                        // Don't generate the assignment here.

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 98746809c83d86c12d2c37b37922548a2d2309d8..809a0fa09a8bc76035f78ee492b3aedb49487a37 100644 (file)
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend {
                        if (f.fail())
                                log_error("Can't open lib file `%s'.\n", filename.c_str());
                        RTLIL::Design *lib = new RTLIL::Design;
-                       Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+                       Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
                        libs.push_back(lib);
                }
 

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index db849882e734501cf9f254a6486b77d96e2b31bb..081dcda999afe06411a48c90166b9a1ce1fa60b1 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -1476,7 +1476,7 @@ struct Smt2Backend : public Backend {
                                int indent = 0;
                                while (indent < GetSize(line) && (line[indent] == ' ' || line[indent] == '\t'))
                                        indent++;
-                               if (line.substr(indent, 2) == "%%")
+                               if (line.compare(indent, 2, "%%") == 0)
                                        break;
                                *f << line << std::endl;
                        }

diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index e9586fae0f5b03a75dc76d8d8b1fbdd5b2ae6d5e..f755307bf6d804ec8500cb708d045c09536af45a 100644 (file)
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -61,7 +61,7 @@ struct SmvWorker
                {
                        string name = stringf("_%s", id.c_str());
 
-                       if (name.substr(0, 2) == "_\\")
+                       if (name.compare(0, 2, "_\\") == 0)
                                name = "_" + name.substr(2);
 
                        for (auto &c : name) {

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6065a71ff7aedaa932e4abd4d1c90fef295889eb..7b1db4776fc15aeb7f93a59ef5dd54b6658ca1e3 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -604,7 +604,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
-       if (cell->type.substr(0, 6) == "$_DFF_")
+       if (cell->type.begins_with("$_DFF_"))
        {
                std::string reg_name = cellname(cell);
                bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
@@ -645,7 +645,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
-       if (cell->type.substr(0, 8) == "$_DFFSR_")
+       if (cell->type.begins_with("$_DFFSR_"))
        {
                char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
 

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index e707f435ad3ccf6fd0f0e0b62a097c64d4f52b48..07ef0a86e839018a54885e20085c837d6b444e0e 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1164,7 +1164,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
                                }
                        }
 
-                       if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
+                       if (flag_icells && (*it)->str.compare(0, 2, "\\$") == 0)
                                (*it)->str = (*it)->str.substr(1);
 
                        if (defer)
@@ -1463,7 +1463,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
 {
        std::string stripped_name = name.str();
 
-       if (stripped_name.substr(0, 9) == "$abstract")
+       if (stripped_name.compare(0, 9, "$abstract") == 0)
                stripped_name = stripped_name.substr(9);
 
        log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 571ddd98886e7c3a4fa9526d37dbd8f0926d6e7e..407a3447213207c8f8f8840bca8d5d289ab1a41e 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1516,7 +1516,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                AstNode *child = *it;
                                if (child->type == AST_CELLTYPE) {
                                        cell->type = child->str;
-                                       if (flag_icells && cell->type.substr(0, 2) == "\\$")
+                                       if (flag_icells && cell->type.begins_with("\\$"))
                                                cell->type = cell->type.substr(1);
                                        continue;
                                }

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 467b2e5c01c1891eebac77972c12b9415b385713..54b9efaada862c7b3abb2993c8882aa821d3027a 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2793,13 +2793,13 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
                std::getline(f, line);
 
                for (int i = 0; i < GetSize(line); i++) {
-                       if (in_comment && line.substr(i, 2) == "*/") {
+                       if (in_comment && line.compare(i, 2, "*/") == 0) {
                                line[i] = ' ';
                                line[i+1] = ' ';
                                in_comment = false;
                                continue;
                        }
-                       if (!in_comment && line.substr(i, 2) == "/*")
+                       if (!in_comment && line.compare(i, 2, "/*") == 0)
                                in_comment = true;
                        if (in_comment)
                                line[i] = ' ';
@@ -2808,7 +2808,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
                while (1)
                {
                        token = next_token(line, " \t\r\n");
-                       if (token.empty() || token.substr(0, 2) == "//")
+                       if (token.empty() || token.compare(0, 2, "//") == 0)
                                break;
 
                        if (token[0] == '@') {

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 06d58a44ab46ad8057d0f9fc478296f9355d04b9..594da45ebc28f15724030cba07831ee3fc12e032 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2140,7 +2140,7 @@ struct VerificPass : public Pass {
                        veri_file::DefineMacro("VERIFIC");
                        veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");
 
-                       for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) {
+                       for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].compare(0, 2, "-D") == 0; argidx++) {
                                std::string name = args[argidx].substr(2);
                                if (args[argidx] == "-D") {
                                        if (++argidx >= GetSize(args))
@@ -2283,7 +2283,7 @@ struct VerificPass : public Pass {
                                break;
                        }
 
-                       if (argidx > GetSize(args) && args[argidx].substr(0, 1) == "-")
+                       if (argidx > GetSize(args) && args[argidx].compare(0, 1, "-") == 0)
                                cmd_error(args, argidx, "unknown option");
 
                        if (mode_all)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0fec445fa4780d53ff46ddda1b7b1ad932641372..4afd72b734b2aadebaf75d86683e8928f29b87e4 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -274,7 +274,7 @@ hierarchical_id:
                $$ = $1;
        } |
        hierarchical_id TOK_PACKAGESEP TOK_ID {
-               if ($3->substr(0, 1) == "\\")
+               if ($3->compare(0, 1, "\\") == 0)
                        *$1 += "::" + $3->substr(1);
                else
                        *$1 += "::" + *$3;
@@ -282,7 +282,7 @@ hierarchical_id:
                $$ = $1;
        } |
        hierarchical_id '.' TOK_ID {
-               if ($3->substr(0, 1) == "\\")
+               if ($3->compare(0, 1, "\\") == 0)
                        *$1 += "." + $3->substr(1);
                else
                        *$1 += "." + *$3;
@@ -2184,7 +2184,7 @@ basic_expr:
                $$ = $1;
        } |
        '(' expr ')' TOK_CONSTVAL {
-               if ($4->substr(0, 1) != "'")
+               if ($4->compare(0, 1, "'") != 0)
                        frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
                AstNode *bits = $2;
                AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
@@ -2194,7 +2194,7 @@ basic_expr:
                delete $4;
        } |
        hierarchical_id TOK_CONSTVAL {
-               if ($2->substr(0, 1) != "'")
+               if ($2->compare(0, 1, "'") != 0)
                        frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
                AstNode *bits = new AstNode(AST_IDENTIFIER);
                bits->str = *$1;

diff --git a/kernel/register.cc b/kernel/register.cc
index e4237cac4aa451187335c391cb03b19b08b43be7..1fd1bad1dd3e92704ac6299439cbcdc7e774eeaa 100644 (file)
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -200,7 +200,7 @@ void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Desig
        {
                std::string arg = args[argidx];
 
-               if (arg.substr(0, 1) == "-")
+               if (arg.compare(0, 1, "-") == 0)
                        cmd_error(args, argidx, "Unknown option or option in arguments.");
 
                if (!select)
@@ -449,7 +449,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
        {
                std::string arg = args[argidx];
 
-               if (arg.substr(0, 1) == "-")
+               if (arg.compare(0, 1, "-") == 0)
                        cmd_error(args, argidx, "Unknown option or option in arguments.");
                if (f != NULL)
                        cmd_error(args, argidx, "Extra filename argument in direct file mode.");
@@ -457,7 +457,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
                filename = arg;
                if (filename == "<<" && argidx+1 < args.size())
                        filename += args[++argidx];
-               if (filename.substr(0, 2) == "<<") {
+               if (filename.compare(0, 2, "<<") == 0) {
                        if (Frontend::current_script_file == NULL)
                                log_error("Unexpected here document '%s' outside of script!\n", filename.c_str());
                        if (filename.size() <= 2)
@@ -475,7 +475,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
                                                break;
                                }
                                size_t indent = buffer.find_first_not_of(" \t\r\n");
-                               if (indent != std::string::npos && buffer.substr(indent, eot_marker.size()) == eot_marker)
+                               if (indent != std::string::npos && buffer.compare(indent, eot_marker.size(), eot_marker) == 0)
                                        break;
                                last_here_document += buffer;
                        }
@@ -522,7 +522,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
                        log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno));
 
                for (size_t i = argidx+1; i < args.size(); i++)
-                       if (args[i].substr(0, 1) == "-")
+                       if (args[i].compare(0, 1, "-") == 0)
                                cmd_error(args, i, "Found option, expected arguments.");
 
                if (argidx+1 < args.size()) {
@@ -612,7 +612,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
        {
                std::string arg = args[argidx];
 
-               if (arg.substr(0, 1) == "-" && arg != "-")
+               if (arg.compare(0, 1, "-") == 0 && arg != "-")
                        cmd_error(args, argidx, "Unknown option or option in arguments.");
                if (f != NULL)
                        cmd_error(args, argidx, "Extra filename argument in direct file mode.");
@@ -625,7 +625,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
 
                filename = arg;
                rewrite_filename(filename);
-               if (filename.size() > 3 && filename.substr(filename.size()-3) == ".gz") {
+               if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".gz") == 0) {
 #ifdef YOSYS_ENABLE_ZLIB
                        gzip_ostream *gf = new gzip_ostream;
                        if (!gf->open(filename)) {

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index a4cc53f1ad8878e48cac6dca813ad0ee59f317e5..5a53f90fddabf71a9098559307a6689ea61bd2c0 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -647,12 +647,12 @@ std::vector<std::string> glob_filename(const std::string &filename_pattern)
 
 void rewrite_filename(std::string &filename)
 {
-       if (filename.substr(0, 1) == "\"" && filename.substr(GetSize(filename)-1) == "\"")
+       if (filename.compare(0, 1, "\"") == 0 && filename.compare(GetSize(filename)-1, std::string::npos, "\"") == 0)
                filename = filename.substr(1, GetSize(filename)-2);
-       if (filename.substr(0, 2) == "+/")
+       if (filename.compare(0, 2, "+/") == 0)
                filename = proc_share_dirname() + filename.substr(2);
 #ifndef _WIN32
-       if (filename.substr(0, 2) == "~/")
+       if (filename.compare(0, 2, "~/") == 0)
                filename = filename.replace(0, 1, getenv("HOME"));
 #endif
 }
@@ -895,25 +895,25 @@ void run_frontend(std::string filename, std::string command, std::string *backen
 
        if (command == "auto") {
                std::string filename_trim = filename;
-               if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".gz")
+               if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0)
                        filename_trim.erase(filename_trim.size()-3);
-               if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-2) == ".v")
+               if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0)
                        command = "verilog";
-               else if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-3) == ".sv")
+               else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
                        command = "verilog -sv";
-               else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".vhd")
+               else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
                        command = "vhdl";
-               else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".blif")
+               else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
                        command = "blif";
-               else if (filename_trim.size() > 5 && filename_trim.substr(filename_trim.size()-6) == ".eblif")
+               else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0)
                        command = "blif";
-               else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".json")
+               else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0)
                        command = "json";
-               else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".il")
+               else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0)
                        command = "ilang";
-               else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".ys")
+               else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0)
                        command = "script";
-               else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".tcl")
+               else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0)
                        command = "tcl";
                else if (filename == "-")
                        command = "script";
@@ -1028,17 +1028,17 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
                design = yosys_design;
 
        if (command == "auto") {
-               if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v")
+               if (filename.size() > 2 && filename.compare(filename.size()-2, std::string::npos, ".v") == 0)
                        command = "verilog";
-               else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
+               else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0)
                        command = "ilang";
-               else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig")
+               else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0)
                        command = "aiger";
-               else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif")
+               else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0)
                        command = "blif";
-               else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif")
+               else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".edif") == 0)
                        command = "edif";
-               else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".json")
+               else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".json") == 0)
                        command = "json";
                else if (filename == "-")
                        command = "ilang";
@@ -1072,7 +1072,7 @@ static char *readline_cmd_generator(const char *text, int state)
        }
 
        for (; it != pass_register.end(); it++) {
-               if (it->first.substr(0, len) == text)
+               if (it->first.compare(0, len, text) == 0)
                        return strdup((it++)->first.c_str());
        }
        return NULL;
@@ -1094,7 +1094,7 @@ static char *readline_obj_generator(const char *text, int state)
                if (design->selected_active_module.empty())
                {
                        for (auto &it : design->modules_)
-                               if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
                                        obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
                }
                else
@@ -1103,19 +1103,19 @@ static char *readline_obj_generator(const char *text, int state)
                        RTLIL::Module *module = design->modules_.at(design->selected_active_module);
 
                        for (auto &it : module->wires_)
-                               if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
                                        obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 
                        for (auto &it : module->memories)
-                               if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
                                        obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 
                        for (auto &it : module->cells_)
-                               if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
                                        obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 
                        for (auto &it : module->processes)
-                               if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
                                        obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
                }
 

diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc
index 1128116b4f24f273a79612d7d46df7124e4ba8bb..628ac4c5e56ec3fa5d0aeaef7873f149f4c57cb4 100644 (file)
--- a/passes/cmds/cover.cc
+++ b/passes/cmds/cover.cc
@@ -121,7 +121,7 @@ struct CoverPass : public Pass {
                        }
                        break;
                }
-               while (argidx < args.size() && args[argidx].substr(0, 1) != "-")
+               while (argidx < args.size() && args[argidx].compare(0, 1, "-") != 0)
                        patterns.push_back(args[argidx++]);
                extra_args(args, argidx, design);
 

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index b5e8ef1afc02bdacd3932aaa6820f52237b97d39..59d10a1b8d8cee8940cc463350c74ca8bd16af27 100644 (file)
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -34,7 +34,7 @@ static bool match_ids(RTLIL::IdString id, std::string pattern)
 {
        if (id == pattern)
                return true;
-       if (id.size() > 0 && id[0] == '\\' && id.substr(1) == pattern)
+       if (id.size() > 0 && id[0] == '\\' && id.compare(1, std::string::npos, pattern.c_str()) == 0)
                return true;
        if (patmatch(pattern.c_str(), id.c_str()))
                return true;
@@ -124,11 +124,11 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, st
        size_t pos = match_expr.find_first_of("<!=>");
 
        if (pos != std::string::npos) {
-               if (match_expr.substr(pos, 2) == "!=")
+               if (match_expr.compare(pos, 2, "!=") == 0)
                        return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '!');
-               if (match_expr.substr(pos, 2) == "<=")
+               if (match_expr.compare(pos, 2, "<=") == 0)
                        return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '[');
-               if (match_expr.substr(pos, 2) == ">=")
+               if (match_expr.compare(pos, 2, ">=") == 0)
                        return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), ']');
                return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+1), match_expr[pos]);
        }
@@ -711,32 +711,32 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
                                log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
                        select_op_alias(design, work_stack[work_stack.size()-1]);
                } else
-               if (arg == "%x" || (arg.size() > 2 && arg.substr(0, 2) == "%x" && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) {
+               if (arg == "%x" || (arg.size() > 2 && arg.compare(0, 2, "%x") == 0 && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) {
                        if (work_stack.size() < 1)
                                log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
                        select_op_expand(design, arg, 'x', false);
                } else
-               if (arg == "%ci" || (arg.size() > 3 && arg.substr(0, 3) == "%ci" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
+               if (arg == "%ci" || (arg.size() > 3 && arg.compare(0, 3, "%ci") == 0 && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
                        if (work_stack.size() < 1)
                                log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
                        select_op_expand(design, arg, 'i', false);
                } else
-               if (arg == "%co" || (arg.size() > 3 && arg.substr(0, 3) == "%co" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
+               if (arg == "%co" || (arg.size() > 3 && arg.compare(0, 3, "%co") == 0 && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
                        if (work_stack.size() < 1)
                                log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
                        select_op_expand(design, arg, 'o', false);
                } else
-               if (arg == "%xe" || (arg.size() > 3 && arg.substr(0, 3) == "%xe" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
+               if (arg == "%xe" || (arg.size() > 3 && arg.compare(0, 3, "%xe") == 0 && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
                        if (work_stack.size() < 1)
                                log_cmd_error("Must have at least one element on the stack for operator %%xe.\n");
                        select_op_expand(design, arg, 'x', true);
                } else
-               if (arg == "%cie" || (arg.size() > 4 && arg.substr(0, 4) == "%cie" && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) {
+               if (arg == "%cie" || (arg.size() > 4 && arg.compare(0, 4, "%cie") == 0 && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) {
                        if (work_stack.size() < 1)
                                log_cmd_error("Must have at least one element on the stack for operator %%cie.\n");
                        select_op_expand(design, arg, 'i', true);
                } else
-               if (arg == "%coe" || (arg.size() > 4 && arg.substr(0, 4) == "%coe" && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) {
+               if (arg == "%coe" || (arg.size() > 4 && arg.compare(0, 4, "%coe") == 0 && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) {
                        if (work_stack.size() < 1)
                                log_cmd_error("Must have at least one element on the stack for operator %%coe.\n");
                        select_op_expand(design, arg, 'o', true);
@@ -766,7 +766,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
        } else {
                size_t pos = arg.find('/');
                if (pos == std::string::npos) {
-                       if (arg.find(':') == std::string::npos || arg.substr(0, 1) == "A")
+                       if (arg.find(':') == std::string::npos || arg.compare(0, 1, "A") == 0)
                                arg_mod = arg;
                        else
                                arg_mod = "*", arg_memb = arg;
@@ -787,7 +787,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
        sel.full_selection = false;
        for (auto &mod_it : design->modules_)
        {
-               if (arg_mod.substr(0, 2) == "A:") {
+               if (arg_mod.compare(0, 2, "A:") == 0) {
                        if (!match_attr(mod_it.second->attributes, arg_mod.substr(2)))
                                continue;
                } else
@@ -800,27 +800,27 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
                }
 
                RTLIL::Module *mod = mod_it.second;
-               if (arg_memb.substr(0, 2) == "w:") {
+               if (arg_memb.compare(0, 2, "w:") == 0) {
                        for (auto &it : mod->wires_)
                                if (match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "i:") {
+               if (arg_memb.compare(0, 2, "i:") == 0) {
                        for (auto &it : mod->wires_)
                                if (it.second->port_input && match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "o:") {
+               if (arg_memb.compare(0, 2, "o:") == 0) {
                        for (auto &it : mod->wires_)
                                if (it.second->port_output && match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "x:") {
+               if (arg_memb.compare(0, 2, "x:") == 0) {
                        for (auto &it : mod->wires_)
                                if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "s:") {
+               if (arg_memb.compare(0, 2, "s:") == 0) {
                        size_t delim = arg_memb.substr(2).find(':');
                        if (delim == std::string::npos) {
                                int width = atoi(arg_memb.substr(2).c_str());
@@ -837,27 +837,27 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
                                                sel.selected_members[mod->name].insert(it.first);
                        }
                } else
-               if (arg_memb.substr(0, 2) == "m:") {
+               if (arg_memb.compare(0, 2, "m:") == 0) {
                        for (auto &it : mod->memories)
                                if (match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "c:") {
+               if (arg_memb.compare(0, 2, "c:") ==0) {
                        for (auto &it : mod->cells_)
                                if (match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "t:") {
+               if (arg_memb.compare(0, 2, "t:") == 0) {
                        for (auto &it : mod->cells_)
                                if (match_ids(it.second->type, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "p:") {
+               if (arg_memb.compare(0, 2, "p:") == 0) {
                        for (auto &it : mod->processes)
                                if (match_ids(it.first, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "a:") {
+               if (arg_memb.compare(0, 2, "a:") == 0) {
                        for (auto &it : mod->wires_)
                                if (match_attr(it.second->attributes, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
@@ -871,12 +871,12 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
                                if (match_attr(it.second->attributes, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else
-               if (arg_memb.substr(0, 2) == "r:") {
+               if (arg_memb.compare(0, 2, "r:") == 0) {
                        for (auto &it : mod->cells_)
                                if (match_attr(it.second->parameters, arg_memb.substr(2)))
                                        sel.selected_members[mod->name].insert(it.first);
                } else {
-                       if (arg_memb.substr(0, 2) == "n:")
+                       if (arg_memb.compare(0, 2, "n:") == 0)
                                arg_memb = arg_memb.substr(2);
                        for (auto &it : mod->wires_)
                                if (match_ids(it.first, arg_memb))
@@ -927,7 +927,7 @@ void handle_extra_select_args(Pass *pass, vector<string> args, size_t argidx, si
 {
        work_stack.clear();
        for (; argidx < args_size; argidx++) {
-               if (args[argidx].substr(0, 1) == "-") {
+               if (args[argidx].compare(0, 1, "-") == 0) {
                        if (pass != NULL)
                                pass->cmd_error(args, argidx, "Unexpected option in selection arguments.");
                        else

diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index b9fcc3e7a3420bd4f081bc45e26afc8f0f5162b3..1ccfc2e86dca143a330a16693fbc4efa7c7d624b 100644 (file)
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -34,7 +34,7 @@ struct setunset_t
 
        setunset_t(std::string set_name, std::string set_value) : name(RTLIL::escape_id(set_name)), value(), unset(false)
        {
-               if (set_value.substr(0, 1) == "\"" && set_value.substr(GetSize(set_value)-1) == "\"") {
+               if (set_value.compare(0, 1, "\"") == 0 && set_value.compare(GetSize(set_value)-1, std::string::npos, "\"") == 0) {
                        value = RTLIL::Const(set_value.substr(1, GetSize(set_value)-2));
                } else {
                        RTLIL::SigSpec sig_value;

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index cf729215fdb0a3caf8f5ffdaccc3a87d38c3d4b5..2e9fc72af18bd6cebc92444558cddf7d35881c06 100644 (file)
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -527,11 +527,11 @@ struct ShowWorker
                {
                        currentColor = xorshift32(currentColor);
                        if (wires_on_demand.count(it.first) > 0) {
-                               if (it.second.in.size() == 1 && it.second.out.size() > 1 && it.second.in.begin()->substr(0, 1) == "p")
+                               if (it.second.in.size() == 1 && it.second.out.size() > 1 && it.second.in.begin()->compare(0, 1, "p") == 0)
                                        it.second.out.erase(*it.second.in.begin());
                                if (it.second.in.size() == 1 && it.second.out.size() == 1) {
                                        std::string from = *it.second.in.begin(), to = *it.second.out.begin();
-                                       if (from != to || from.substr(0, 1) != "p")
+                                       if (from != to || from.compare(0, 1, "p") != 0)
                                                fprintf(f, "%s:e -> %s:w [%s, %s];\n", from.c_str(), to.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
                                        continue;
                                }
@@ -808,7 +808,7 @@ struct ShowPass : public Pass {
                        if (f.fail())
                                log_error("Can't open lib file `%s'.\n", filename.c_str());
                        RTLIL::Design *lib = new RTLIL::Design;
-                       Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+                       Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
                        libs.push_back(lib);
                }
 

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 3596dfd7b87d7503e8d1dc083ac04234ba0a61d9..19d1c25acbfcc9fe2cac6d6fb5513d636ee75d97 100644 (file)
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -97,7 +97,7 @@ struct EquivOptPass:public ScriptPass
 
                for (; argidx < args.size(); argidx++) {
                        if (command.empty()) {
-                               if (args[argidx].substr(0, 1) == "-")
+                               if (args[argidx].compare(0, 1, "-") == 0)
                                        cmd_error(args, argidx, "Unknown option.");
                        } else {
                                command += " ";

diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index a7973fd04e4adb2c5331e9171fa7802f400730e4..6672948b92d4799c2bb108739a1b3cc137da210f 100644 (file)
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -215,9 +215,9 @@ struct EquivStructWorker
                                        if (c != nullptr) {
                                                string n = cell_name.str();
                                                cells_type = c->type;
-                                               if (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gold")
+                                               if (GetSize(n) > 5 && n.compare(GetSize(n)-5, std::string::npos, "_gold") == 0)
                                                        gold_cells.push_back(c);
-                                               else if (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gate")
+                                               else if (GetSize(n) > 5 && n.compare(GetSize(n)-5, std::string::npos, "_gate") == 0)
                                                        gate_cells.push_back(c);
                                                else
                                                        other_cells.push_back(c);

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index a8a8e0bc7812ca472c00fb6426164758b711d964..905c95b6c8d0c83010d45facfe8d34231967ee07 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -222,10 +222,10 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 
 bool check_public_name(RTLIL::IdString id)
 {
-       const std::string &id_str = id.str();
-       if (id_str[0] == '$')
+       if (id.begins_with("$"))
                return false;
-       if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos))
+       const std::string &id_str = id.str();
+       if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
                return false;
        if (id_str.find(".$") != std::string::npos)
                return false;

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 8964171e61144350e1f73bd7a8a2be66286a03a4..cac7c0a6f2d928a35adbe551028c2f8efa7b5578 100644 (file)
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,7 +222,7 @@ struct OptMergeWorker
                        return true;
                }
 
-               if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
+               if (cell1->type.begins_with("$") && conn1.count("\\Q") != 0) {
                        std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
                        std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
                        for (size_t i = 0; i < q1.size(); i++)

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 450626f4a9ee8567e705cbb209c09ae9db850747..8d42a37c3a8f3d46f0f2975f8da369faeb4cce35 100644 (file)
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
                sig_c = dff->getPort("\\C");
                val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
        }
-       else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" &&
+       else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
                        (dff->type[6] == 'N' || dff->type[6] == 'P') &&
                        (dff->type[7] == 'N' || dff->type[7] == 'P') &&
                        (dff->type[8] == '0' || dff->type[8] == '1')) {
@@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
                val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
                val_rv = RTLIL::Const(dff->type[8] == '1', 1);
        }
-       else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" &&
+       else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
                        (dff->type[7] == 'N' || dff->type[7] == 'P') &&
                        (dff->type[8] == 'N' || dff->type[8] == 'P')) {
                sig_d = dff->getPort("\\D");

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 71ce1683d95b9d9842147a4acf8dad07acc477f1..7631d87e69dbc302534a247086dd99b28943974a 100644 (file)
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -151,7 +151,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
                        continue;
                }
 
-               if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
+               if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) {
                        info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
                        info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
                        info.clk_polarity = info.cell->type[6] == 'P';

diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index e1da1a9e697619cceefe36a8a05dd18fb29339ea..49ef4006156ab6fd8c8f252b0f080434ed765d8c 100644 (file)
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -59,7 +59,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
                }
                break;
        }
-       if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-")
+       if (argidx+3 != args.size() || args[argidx].compare(0, 1, "-") == 0)
                that->cmd_error(args, argidx, "command argument error");
 
        RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]);
@@ -279,7 +279,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
                }
                break;
        }
-       if ((argidx+1 != args.size() && argidx+2 != args.size()) || args[argidx].substr(0, 1) == "-")
+       if ((argidx+1 != args.size() && argidx+2 != args.size()) || args[argidx].compare(0, 1, "-") == 0)
                that->cmd_error(args, argidx, "command argument error");
 
        IdString module_name = RTLIL::escape_id(args[argidx++]);

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index e4654d83549383dca604b774b74a1539ce2df3f8..dd56d8c71197d0e4f80952e92b6d352b37f2e2d2 100644 (file)
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -519,7 +519,7 @@ struct SatHelper
                                        for (auto &p : d->connections()) {
                                                if (d->type == "$dff" && p.first == "\\CLK")
                                                        continue;
-                                               if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C")
+                                               if (d->type.begins_with("$_DFF_") && p.first == "\\C")
                                                        continue;
                                                queued_signals.add(handled_signals.remove(sigmap(p.second)));
                                        }
@@ -797,7 +797,7 @@ struct SatHelper
 
                        vector<string> data;
                        string name = wd.first.c_str();
-                       while (name.substr(0, 1) == "\\")
+                       while (name.compare(0, 1, "\\") == 0)
                                name = name.substr(1);
 
                        fprintf(f, "    { \"name\": \"%s\", \"wave\": \"", name.c_str());
@@ -1353,7 +1353,7 @@ struct SatPass : public Pass {
                if (show_regs) {
                        pool<Wire*> reg_wires;
                        for (auto cell : module->cells()) {
-                               if (cell->type == "$dff" || cell->type.substr(0, 6) == "$_DFF_")
+                               if (cell->type == "$dff" || cell->type.begins_with("$_DFF_"))
                                        for (auto bit : cell->getPort("\\Q"))
                                                if (bit.wire)
                                                        reg_wires.insert(bit.wire);

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 7cb784505856986c69b831e7e7fab4b6110d4faf..9db8aafa7cf90a3d578b895df7ccc01c32e11906 100644 (file)
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -333,12 +333,12 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
 {
        std::string abc_sname = abc_name.substr(1);
        bool isnew = false;
-       if (abc_sname.substr(0, 4) == "new_")
+       if (abc_sname.compare(0, 4, "new_") == 0)
        {
                abc_sname.erase(0, 4);
                isnew = true;
        }
-       if (abc_sname.substr(0, 5) == "ys__n")
+       if (abc_sname.compare(0, 5, "ys__n") == 0)
        {
                abc_sname.erase(0, 5);
                if (std::isdigit(abc_sname.at(0)))
@@ -1562,10 +1562,10 @@ struct AbcPass : public Pass {
                                size_t pos = arg.find_first_of(':');
                                int lut_mode = 0, lut_mode2 = 0;
                                if (pos != string::npos) {
-                                       lut_mode = std::atoi(arg.substr(0, pos).c_str());
-                                       lut_mode2 = std::atoi(arg.substr(pos+1).c_str());
+                                       lut_mode = atoi(arg.substr(0, pos).c_str());
+                                       lut_mode2 = atoi(arg.substr(pos+1).c_str());
                                } else {
-                                       lut_mode = std::atoi(arg.c_str());
+                                       lut_mode = atoi(arg.c_str());
                                        lut_mode2 = lut_mode;
                                }
                                lut_costs.clear();

diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 2dc577c73edaaaaffdfbb0cdaf67d4d85c60a8b6..c0bf3a6658652a06d14ea8fba53b2850d35bcf9c 100644 (file)
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -377,7 +377,7 @@ struct Dff2dffePass : public Pass {
                                                        mod->remove(cell);
                                                        continue;
                                                }
-                                               if (cell->type.substr(0, 7) == "$_DFFE_") {
+                                               if (cell->type.begins_with("$_DFFE_")) {
                                                        if (min_ce_use >= 0) {
                                                                int ce_use = 0;
                                                                for (auto cell_other : mod->selected_cells()) {
@@ -390,8 +390,8 @@ struct Dff2dffePass : public Pass {
                                                                        continue;
                                                        }
 
-                                                       bool clk_pol = cell->type.substr(7, 1) == "P";
-                                                       bool en_pol = cell->type.substr(8, 1) == "P";
+                                                       bool clk_pol = cell->type.compare(7, 1, "P") == 0;
+                                                       bool en_pol = cell->type.compare(8, 1, "P") == 0;
                                                        RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
                                                        mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol);
                                                        if (en_pol)

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index fff90f13c29018ed58994c1514d462a64845b648..e3b4faba15fbed3644483105f19502c7b9b57234 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -54,7 +54,7 @@ public:
 
        RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value)
        {
-               if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_")
+               if (!cell_type.begins_with("$") || cell_type.begins_with("$_"))
                        return value;
 
        #define param_bool(_n) if (param == _n) return value.as_bool();
@@ -203,7 +203,7 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
                        continue;
 
                std::string type = cell->type.str();
-               if (sel == NULL && type.substr(0, 2) == "\\$")
+               if (sel == NULL && type.compare(0, 2, "\\$") == 0)
                        type = type.substr(1);
                graph.createNode(cell->name.str(), type, (void*)cell);
 
@@ -594,7 +594,7 @@ struct ExtractPass : public Pass {
                        map = new RTLIL::Design;
                        for (auto &filename : map_filenames)
                        {
-                               if (filename.substr(0, 1) == "%")
+                               if (filename.compare(0, 1, "%") == 0)
                                {
                                        if (!saved_designs.count(filename.substr(1))) {
                                                delete map;
@@ -613,10 +613,10 @@ struct ExtractPass : public Pass {
                                                delete map;
                                                log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
                                        }
-                                       Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+                                       Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
                                        f.close();
 
-                                       if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
+                                       if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) {
                                                Pass::call(map, "proc");
                                                Pass::call(map, "opt_clean");
                                        }

diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 45987392e2597b54d3de36a54ba9dcda0dbfc36a..81546249ce19e4d0afa2adc86288dd6ce7f43e96 100644 (file)
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -675,11 +675,11 @@ struct MuxcoverPass : public Pass {
                for (argidx = 1; argidx < args.size(); argidx++)
                {
                        const auto &arg = args[argidx];
-                       if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") {
+                       if (arg.size() >= 6 && arg.compare(0,6,"-mux2=") == 0) {
                                cost_mux2 = atoi(arg.substr(6).c_str());
                                continue;
                        }
-                       if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
+                       if (arg.size() >= 5 && arg.compare(0,5,"-mux4") == 0) {
                                use_mux4 = true;
                                if (arg.size() > 5) {
                                        if (arg[5] != '=') break;
@@ -687,7 +687,7 @@ struct MuxcoverPass : public Pass {
                                }
                                continue;
                        }
-                       if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") {
+                       if (arg.size() >= 5 && arg.compare(0,5,"-mux8") == 0) {
                                use_mux8 = true;
                                if (arg.size() > 5) {
                                        if (arg[5] != '=') break;
@@ -695,7 +695,7 @@ struct MuxcoverPass : public Pass {
                                }
                                continue;
                        }
-                       if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") {
+                       if (arg.size() >= 6 && arg.compare(0,6,"-mux16") == 0) {
                                use_mux16 = true;
                                if (arg.size() > 6) {
                                        if (arg[6] != '=') break;
@@ -703,7 +703,7 @@ struct MuxcoverPass : public Pass {
                                }
                                continue;
                        }
-                       if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
+                       if (arg.size() >= 6 && arg.compare(0,6,"-dmux=") == 0) {
                                cost_dmux = atoi(arg.substr(6).c_str());
                                continue;
                        }

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index ceb0538255a12c919b3a64d14cdd0b04b7a16513..2708b08aed756d9acad5346a68eb657656ba8a72 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -243,7 +243,7 @@ struct TechmapWorker
                        if (positional_ports.count(portname) > 0)
                                portname = positional_ports.at(portname);
                        if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
-                               if (portname.substr(0, 1) == "$")
+                               if (portname.begins_with("$"))
                                        log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
                                continue;
                        }
@@ -341,7 +341,7 @@ struct TechmapWorker
                        RTLIL::Cell *c = module->addCell(c_name, it.second);
                        design->select(module, c);
 
-                       if (!flatten_mode && c->type.substr(0, 2) == "\\$")
+                       if (!flatten_mode && c->type.begins_with("\\$"))
                                c->type = c->type.substr(1);
 
                        for (auto &it2 : c->connections_) {
@@ -406,7 +406,7 @@ struct TechmapWorker
                                continue;
 
                        std::string cell_type = cell->type.str();
-                       if (in_recursion && cell_type.substr(0, 2) == "\\$")
+                       if (in_recursion && cell->type.begins_with("\\$"))
                                cell_type = cell_type.substr(1);
 
                        if (celltypeMap.count(cell_type) == 0) {
@@ -468,7 +468,7 @@ struct TechmapWorker
 
                        std::string cell_type = cell->type.str();
 
-                       if (in_recursion && cell_type.substr(0, 2) == "\\$")
+                       if (in_recursion && cell->type.begins_with("\\$"))
                                cell_type = cell_type.substr(1);
 
                        for (auto &tpl_name : celltypeMap.at(cell_type))
@@ -602,7 +602,7 @@ struct TechmapWorker
                                        }
 
                                        for (auto conn : cell->connections()) {
-                                               if (conn.first.substr(0, 1) == "$")
+                                               if (conn.first.begins_with("$"))
                                                        continue;
                                                if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
                                                        continue;
@@ -725,7 +725,7 @@ struct TechmapWorker
 
                                                for (auto &it : twd)
                                                {
-                                                       if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
+                                                       if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
                                                                continue;
 
                                                        auto &data = it.second.front();
@@ -874,7 +874,7 @@ struct TechmapWorker
                                                tpl->cloneInto(m);
 
                                                for (auto cell : m->cells()) {
-                                                       if (cell->type.substr(0, 2) == "\\$")
+                                                       if (cell->type.begins_with("\\$"))
                                                                cell->type = cell->type.substr(1);
                                                }
 
@@ -1113,7 +1113,7 @@ struct TechmapPass : public Pass {
                        Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
                } else {
                        for (auto &fn : map_files)
-                               if (fn.substr(0, 1) == "%") {
+                               if (fn.compare(0, 1, "%") == 0) {
                                        if (!saved_designs.count(fn.substr(1))) {
                                                delete map;
                                                log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
@@ -1128,7 +1128,7 @@ struct TechmapPass : public Pass {
                                        yosys_input_files.insert(fn);
                                        if (f.fail())
                                                log_cmd_error("Can't open map file `%s'\n", fn.c_str());
-                                       Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
+                                       Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
                                }
                }
 
@@ -1143,7 +1143,7 @@ struct TechmapPass : public Pass {
                                free(p);
                        } else {
                                string module_name = it.first.str();
-                               if (module_name.substr(0, 2) == "\\$")
+                               if (it.first.begins_with("\\$"))
                                        module_name = module_name.substr(1);
                                celltypeMap[module_name].insert(it.first);
                        }

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index cea247dc7dfd8c86cfde9446ece2dd2b486afd11..31966995570d37d3eae7343c9cdbd23eb8162a17 100644 (file)
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -872,7 +872,7 @@ struct TestCellPass : public Pass {
                                continue;
                        }
 
-                       if (args[argidx].substr(0, 1) == "/") {
+                       if (args[argidx].compare(0, 1, "/") == 0) {
                                std::vector<std::string> new_selected_cell_types;
                                for (auto it : selected_cell_types)
                                        if (it != args[argidx].substr(1))

diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 4fa6b0792ed11bee3f99f1e98a8b455576522cd0..1a139ffea7a3469cb1ec947bdf396409279c7147 100644 (file)
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
 
                        for (int i = 0; i < GetSize(line); i++)
                        {
-                               if (in_comment && line.substr(i, 2) == "*/") {
+                               if (in_comment && line.compare(i, 2, "*/") == 0) {
                                        line[i] = ' ';
                                        line[i+1] = ' ';
                                        in_comment = false;
                                        continue;
                                }
-                               if (!in_comment && line.substr(i, 2) == "/*")
+                               if (!in_comment && line.compare(i, 2, "/*") == 0)
                                        in_comment = true;
                                if (in_comment)
                                        line[i] = ' ';
@@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
                                long value;
 
                                token = next_token(line, " \t\r\n");
-                               if (token.empty() || token.substr(0, 2) == "//")
+                               if (token.empty() || token.compare(0, 2, "//") == 0)
                                        break;
 
                                if (token[0] == '@') {