* x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+.

From-SVN: r254343

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb46f71ce775bd60e6dd900556ae21eee8c77a4b..067164afb7170bf34c3556f9840890f1f1be1c0d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-11-02  Jan Hubicka  <hubicka@ucw.cz>
+
+       * x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+.
+
 2017-11-02  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/82795

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index c7099d7d78bd3e63553d289751895be85bf1f04e..99282c883410a9085fdbc6a75b44c18e7655128b 100644 (file)
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -220,10 +220,15 @@ DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
    as "add mem, reg".  */
 DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
 
-/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.   */
+/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
+
+   Core2 and nehalem has stall of 7 cycles for partial flag register stalls.
+   Sandy bridge and Ivy bridge generate extra uop.  On Haswell this extra uop
+   is output only when the values needs to be really merged, which is not
+   done by GCC generated code.  */
 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
-          ~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
-          |  m_KNL | m_KNM | m_GENERIC))
+          ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
+           | m_BONNELL | m_SILVERMONT | m_INTEL |  m_KNL | m_KNM | m_GENERIC))
 
 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
    for DFmode copies */