/* Sanity check */
 
-        unsigned total_size = header_size + body_size;
-
         if (t.hierarchy_mask) {
-                assert(ctx->tiler_polygon_list.bo->size >= total_size);
+                assert(ctx->tiler_polygon_list.bo->size >= (header_size + body_size));
 
                 /* Specify allocated tiler structures */
                 t.polygon_list = ctx->tiler_polygon_list.bo->gpu;
         struct panfrost_sampler_view *view)
 {
         if (!view)
-                return (mali_ptr) NULL;
+                return (mali_ptr) 0;
 
         struct pipe_sampler_view *pview = &view->base;
         struct panfrost_resource *rsrc = pan_resource(pview->texture);
 
 {
         struct panfrost_bo *bo = rzalloc(screen, struct panfrost_bo);
         struct drm_panfrost_get_bo_offset get_bo_offset = {0,};
-        int ret;
+        MAYBE_UNUSED int ret;
         unsigned gem_handle;
 
         ret = drmPrimeFDToHandle(screen->fd, fd, &gem_handle);
 int
 panfrost_drm_submit_vs_fs_job(struct panfrost_context *ctx, bool has_draws, bool is_scanout)
 {
-        int ret;
+        int ret = 0;
 
         struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
 
 panfrost_drm_query_gpu_version(struct panfrost_screen *screen)
 {
         struct drm_panfrost_get_param get_param = {0,};
-        int ret;
+        MAYBE_UNUSED int ret;
 
         get_param.param = DRM_PANFROST_PARAM_GPU_PROD_ID;
         ret = drmIoctl(screen->fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
 
         struct pipe_surface *surf)
 {
         struct panfrost_resource *rsrc = pan_resource(surf->texture);
-        enum pipe_format format = surf->format;
 
         unsigned level = surf->u.tex.level;
         assert(surf->u.tex.first_layer == 0);
         if (rsrc->layout == PAN_AFBC) {
                 /* The only Z/S format we can compress is Z24S8 or variants
                  * thereof (handled by the state tracker) */
-                assert(format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
+                assert(surf->format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
 
                 mali_ptr base = rsrc->bo->gpu + offset;
                 unsigned header_size = rsrc->slices[level].header_size;
         } else if (rsrc->layout == PAN_LINEAR) {
                 /* TODO: Z32F(S8) support, which is always linear */
 
-                assert(format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
+                assert(surf->format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
                 int stride = rsrc->slices[level].stride;
                 fb->mfbd_flags |= MALI_MFBD_EXTRA;
 
 
 static void
 emit_sysval_read(compiler_context *ctx, nir_instr *instr)
 {
-        unsigned dest;
+        unsigned dest = 0;
+
         /* Figure out which uniform this is */
         int sysval = sysval_for_instr(ctx, instr, &dest);
         void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);