(no commit message)

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 24e522f6d9a9e7365d6dbebde86d4562aa35cb1e..521a42c77df4f3b7c045ae1c07ec9fe0ed000904 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -99,16 +99,16 @@ TODO: convert all instructions to use RT and not RS
 | NN | RT | RA  | RB   | /BFA/   | 0  01  00 |1 | bincrflut  | VA-Form     |
 | NN |    |     |      |         | 1  01  00 |1 | rsvd    |           |
 | NN |    |     |      |         | -  10  00 |1 | rsvd    |           |
-| NN |    |     |      |         | 0  11  00 |1 | svshape    |           |
-| NN |    |     |      |         | 1  11  00 |1 | svstep   |           |
+| NN |    |     |      |         | 0  11  00 |1 | svshape    | SVM-Form    |
+| NN |    |     |      |         | 1  11  00 |1 | svremap   | SVRM-Form   |
 | NN | RT | RA  | RB   | im0-4   | im5-7  01 |0 | grevlog |  TLI-Form    |
 | NN | RT | RA  | RB   | im0-4   | im5-7  01 |1 | grevlogw |   TLI-Form  |
 | NN | RT | RA  | RB   | RC      | mode  010 |Rc| bitmask\* |  VA2-Form    |
 | NN |    |     |      |         | 0-    011 |  | rsvd    |           |
-| NN |    |     |      |         | 10    011 |Rc| svstep |           |
-| NN |    |     |      |         | 11    011 |Rc| setvl |           |
+| NN |    |     |      |         | 10    011 |Rc| svstep |  SVL-Form     |
+| NN |    |     |      |         | 11    011 |Rc| setvl |   SVL-Form        |
 | NN |    |     |      |         | ----  110 |  | 1/2 ops | other table |
-| NN | RT | RA  | RB   | sh0-4   | sh5 1 111 |Rc| bmrevi |           |
+| NN | RT | RA  | RB   | sh0-4   | sh5 1 111 |Rc| bmrevi |  XB-Form    |
 
 ops (note that av avg and abs as well as vec scalar mask
 are included here [[sv/vector_ops]], and