/* Create the backing buffer if needed. */
if (!tex->buf) {
tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
- tex->domain, 0);
+ tex->domain, RADEON_FLAG_HANDLE);
if (!tex->buf) {
goto fail;
r600_init_resource_fields(rscreen, resource, rtex->size,
rtex->surface.bo_alignment);
+ resource->flags |= RADEON_FLAG_HANDLE;
+
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);
return NULL;
RADEON_FLAG_GTT_WC = (1 << 0),
RADEON_FLAG_CPU_ACCESS = (1 << 1),
RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
+ RADEON_FLAG_HANDLE = (1 << 3), /* the buffer most not be suballocated */
};
enum radeon_bo_usage { /* bitfield */
struct amdgpu_winsys_bo *bo;
unsigned usage = 0, pb_cache_bucket;
+ /* This flag is irrelevant for the cache. */
+ flags &= ~RADEON_FLAG_HANDLE;
+
/* Align size to page size. This is the minimum alignment for normal
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
if (size > UINT_MAX)
return NULL;
+ /* This flag is irrelevant for the cache. */
+ flags &= ~RADEON_FLAG_HANDLE;
+
/* Align size to page size. This is the minimum alignment for normal
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
/* Create a fence, which is a dummy BO. */
fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1,
- RADEON_DOMAIN_GTT, 0);
+ RADEON_DOMAIN_GTT, RADEON_FLAG_HANDLE);
/* Add the fence as a dummy relocation. */
cs->ws->base.cs_add_buffer(rcs, fence,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT,