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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 6f23727ba054565a4b2724b4b74003637bff07f0..600e68de7024a717799ebb379a5767414a2ab428 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -740,20 +740,28 @@ overrides not included.  if there is no predicate, it is set to all 1s
     function op_add(rd, rs1, rs2) # add not VADD!
       int i, id=0, irs1=0, irs2=0; predval = get_pred_val(FALSE, rd);
       for (i = 0; i < VL; i++)
-        STATE.srcoffs = i # save context if (predval & 1<<i) # predication
-        uses intregs
-           ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2]; if (!int_vec[rd
-           ].isvec) break;
-        if (rd.isvec)  { id += 1; } if (rs1.isvec)  { irs1 += 1; } if
-        (rs2.isvec)  { irs2 += 1; } if (id == VL or irs1 == VL or irs2 ==
-        VL) {
-          # end VL hardware loop STATE.srcoffs = 0; # reset return;
+        STATE.srcoffs = i # save context
+        if (predval & 1<<i) # predication uses intregs
+           ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
+        if (!int_vec[rd].isvec) break;
+        if (rd.isvec)  { id += 1; }
+        if (rs1.isvec) { irs1 += 1; }
+        if (rs2.isvec) { irs2 += 1; }
+        if (id == VL or irs1 == VL or irs2 == VL)
+        {
+          # end VL hardware loop
+          STATE.srcoffs = 0; # reset
+          return;
         }
 
 This has several modes:
 
-* RT.v = RA.v RB.v * RT.v = RA.v RB.s (and RA.s RB.v) * RT.v = RA.s RB.s *
-RT.s = RA.v RB.v * RT.s = RA.v RB.s (and RA.s RB.v) * RT.s = RA.s RB.s
+* RT.v = RA.v RB.v
+* RT.v = RA.v RB.s (and RA.s RB.v)
+* RT.v = RA.s RB.s
+* RT.s = RA.v RB.v
+* RT.s = RA.v RB.s (and RA.s RB.v)
+* RT.s = RA.s RB.s
 
 All of these may be predicated.  Vector-Vector is straightfoward.
 When one of source is a Vector and the other a Scalar, it is clear that