Fix PR87374: ICE with -mslow-flash-data and -mword-relocations

GCC ICEs under -mslow-flash-data and -mword-relocations because there
is no way to load an address, both literal pools and MOVW/MOVT being
forbidden. This patch gives an error message when both options are
specified by the user and adds the according dg-skip-if directives for
tests that use either of these options. It also explicitely set the
option when in PIC mode as per documentation rather than always check
for target_word_relocation together with flag_pic.

2018-10-31  Thomas Preud'homme  <thomas.preudhomme@linaro.org>

    gcc/
    PR target/87374
    * config/arm/arm.c (arm_option_check_internal): Disable the combined
    use of -mslow-flash-data and -mword-relocations.
    (arm_option_override): Enable -mword-relocations if -fpic or -fPIC.
    * config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for
    flag_pic.
    * doc/invoke.texi (-mword-relocations): Mention conflict with
    -mslow-flash-data.
    (-mslow-flash-data): Reciprocally.

    gcc/testsuite/
    PR target/87374
    * gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and
    -mword-relocations would be passed when compiling the test.
    * gcc.target/arm/movsi_movt.c: Likewise.
    * gcc.target/arm/pr81863.c: Likewise.
    * gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise.
    * gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise.
    * gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise.
    * gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise.
    * gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise.
    * gcc.target/arm/tls-disable-literal-pool.c: Likewise.

From-SVN: r265662

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1587a51b4b69e3b1a0ddb1862757db0f1e3f3d98..de50a8fe5644597541063d269ff26b040de5a030 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2018-10-31  Thomas Preud'homme  <thomas.preudhomme@linaro.org>
+
+       PR target/87374
+       * config/arm/arm.c (arm_option_check_internal): Disable the combined
+       use of -mslow-flash-data and -mword-relocations.
+       (arm_option_override): Enable -mword-relocations if -fpic or -fPIC.
+       * config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for
+       flag_pic.
+       * doc/invoke.texi (-mword-relocations): Mention conflict with
+       -mslow-flash-data.
+       (-mslow-flash-data): Reciprocally.
+
 2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
 
        * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 8810df53aa34798b5e3e1eb3a870101d530702e4..8393f0b87f34c04c9dcc89c63d2e9bbd042c969c 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2893,17 +2893,22 @@ arm_option_check_internal (struct gcc_options *opts)
       flag_pic = 0;
     }
 
-  /* We only support -mpure-code and -mslow-flash-data on M-profile targets
-     with MOVT.  */
-  if ((target_pure_code || target_slow_flash_data)
-      && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
+  if (target_pure_code || target_slow_flash_data)
     {
       const char *flag = (target_pure_code ? "-mpure-code" :
                                             "-mslow-flash-data");
-      error ("%s only supports non-pic code on M-profile targets with the "
-            "MOVT instruction", flag);
-    }
 
+      /* We only support -mpure-code and -mslow-flash-data on M-profile targets
+        with MOVT.  */
+      if (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON)
+       error ("%s only supports non-pic code on M-profile targets with the "
+              "MOVT instruction", flag);
+
+      /* Cannot load addresses: -mslow-flash-data forbids literal pool and
+        -mword-relocations forbids relocation of MOVT/MOVW.  */
+      if (target_word_relocations)
+       error ("%s incompatible with -mword-relocations", flag);
+    }
 }
 
 /* Recompute the global settings depending on target attribute options.  */
@@ -3489,6 +3494,9 @@ arm_option_override (void)
        arm_pic_register = pic_register;
     }
 
+  if (flag_pic)
+    target_word_relocations = 1;
+
   /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores.  */
   if (fix_cm3_ldrd == 2)
     {

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 270b8e454b3431b81d20fc26506c2c043933b09b..a773518cefaf8451e77fead9e072ee8ef39f1eb8 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6128,7 +6128,7 @@
   [(set (match_operand:SI 0 "arm_general_register_operand" "")
        (match_operand:SI 1 "general_operand" ""))]
   "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
-   && !flag_pic && !target_word_relocations
+   && !target_word_relocations
    && !arm_tls_referenced_p (operands[1])"
   [(clobber (const_int 0))]
 {

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 055e8c4759c7f7d044188ea41050fb3031697a07..3d83bf56cafa9cb8bdb7682078a75462da8bf4da 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17034,7 +17034,7 @@ this option and always use the original scheme.
 Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).
 This is enabled by default on targets (uClinux, SymbianOS) where the runtime
 loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
-is specified.
+is specified. This option conflicts with @option{-mslow-flash-data}.
 
 @item -mfix-cortex-m3-ldrd
 @opindex mfix-cortex-m3-ldrd
@@ -17071,7 +17071,7 @@ to Neon is high.
 Assume loading data from flash is slower than fetching instruction.
 Therefore literal load is minimized for better performance.
 This option is only supported when compiling for ARMv7 M-profile and
-off by default.
+off by default. It conflicts with @option{-mword-relocations}.
 
 @item -masm-syntax-unified
 @opindex masm-syntax-unified

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4ca1d26c68bcb6f8a97fdc468b7b2f7d7ed3534e..74e1ece85300ec2901752fe083ff8543709bcf21 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2018-10-31  Thomas Preud'homme  <thomas.preudhomme@linaro.org>
+
+       PR target/87374
+       * gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and
+       -mword-relocations would be passed when compiling the test.
+       * gcc.target/arm/movsi_movt.c: Likewise.
+       * gcc.target/arm/pr81863.c: Likewise.
+       * gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise.
+       * gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise.
+       * gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise.
+       * gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise.
+       * gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise.
+       * gcc.target/arm/tls-disable-literal-pool.c: Likewise.
+
 2018-10-31  Richard Biener  <rguenther@suse.de>
 
        PR testsuite/87802

diff --git a/gcc/testsuite/gcc.target/arm/movdi_movt.c b/gcc/testsuite/gcc.target/arm/movdi_movt.c
index e2a28ccbd994ed0e4d0b9ac432df32138820432c..a01ffa0dc933d14678fc43e70c7dbe61eca4584b 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/movdi_movt.c
+++ b/gcc/testsuite/gcc.target/arm/movdi_movt.c
@@ -1,4 +1,5 @@
 /* { dg-do compile { target { arm_cortex_m && { arm_thumb2_ok || arm_thumb1_movt_ok } } } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-O2 -mslow-flash-data" } */
 
 unsigned long long

diff --git a/gcc/testsuite/gcc.target/arm/movsi_movt.c b/gcc/testsuite/gcc.target/arm/movsi_movt.c
index 3cf46e2fd172ee1728b7b50c1cead90924962dca..19d202ecd330574432f13fd003586815b5efc8d3 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/movsi_movt.c
+++ b/gcc/testsuite/gcc.target/arm/movsi_movt.c
@@ -1,4 +1,5 @@
 /* { dg-do compile { target { arm_cortex_m && { arm_thumb2_ok || arm_thumb1_movt_ok } } } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-O2 -mslow-flash-data" } */
 
 unsigned

diff --git a/gcc/testsuite/gcc.target/arm/pr81863.c b/gcc/testsuite/gcc.target/arm/pr81863.c
index 63b1ed66b2c736c8dc9436d8251cf72c5d31adb3..225a0c5cc2b358416ec2dea14b11bb4f726e0649 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/pr81863.c
+++ b/gcc/testsuite/gcc.target/arm/pr81863.c
@@ -1,5 +1,6 @@
 /* testsuite/gcc.target/arm/pr48183.c */
 /* { dg-do compile } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mslow-flash-data" } } */
 /* { dg-options "-O2 -mword-relocations -march=armv7-a -marm" } */
 /* { dg-final { scan-assembler-not "\[\\t \]+movw" } } */
 

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
index 089a72b67f3af570dbbed248a64a18b8b4e89ba4..d10391a69ac0cfa5c9cbee877e7235e2c240a591 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
@@ -6,6 +6,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_cortex_m } */
 /* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-O2 -mthumb -mslow-flash-data" } */
 
 float sf;

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
index c87e050639d098e8a228dacc8e64efafe9eb4861..90bd44e27e5c53d34f2816f4d6320acbc1dc709b 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
@@ -3,6 +3,7 @@
 /* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
 /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
 
 float f (float);

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
index 8c6210ee6c9e702da92222b9fe471b3f3bbb3a3b..5d9cd9c4df28837b81b2de48c25d38cdf2c15999 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
@@ -3,6 +3,7 @@
 /* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
 /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -mthumb -mslow-flash-data" } */
 
 /* From PR71607 */

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
index 1bcb6924ed2aa15ba2b0dc0968cad743322e5147..0eeddd5e6ec1f42a96fc6220277f9ecb7cad44f5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
@@ -3,6 +3,7 @@
 /* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
 /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
 
 double __attribute__ ((target ("fpu=fpv5-d16")))

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
index 808fff05faaada2567c9ad02a2ab50ed744d1782..7d52f3801b6d4b62b27833871ac830d6d077894d 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
@@ -3,6 +3,7 @@
 /* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
 /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
 
 double __attribute__ ((target ("fpu=fpv5-sp-d16")))

diff --git a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
index 283201fdd97aac2fcd302665b519a27615558364..834eaf6db92c0239deb397c7d002086d83577be2 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
+++ b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
@@ -2,6 +2,7 @@
 /* { dg-require-effective-target tls_native } */
 /* { dg-require-effective-target arm_cortex_m } */
 /* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
 /* { dg-options "-mslow-flash-data" } */
 
 __thread int x = 0;