HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (src, 0, i), 1));
enum machine_mode mode = GET_MODE (tmps[i]);
unsigned int bytelen = GET_MODE_SIZE (mode);
+ rtx dest = dst;
/* Handle trailing fragments that run over the size of the struct. */
if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize)
bytelen = ssize - bytepos;
}
+ if (GET_CODE (dst) == CONCAT)
+ {
+ if (bytepos + bytelen <= GET_MODE_SIZE (GET_MODE (XEXP (dst, 0))))
+ dest = XEXP (dst, 0);
+ else if (bytepos >= GET_MODE_SIZE (GET_MODE (XEXP (dst, 0))))
+ {
+ bytepos -= GET_MODE_SIZE (GET_MODE (XEXP (dst, 0)));
+ dest = XEXP (dst, 1);
+ }
+ else
+ abort ();
+ }
+
/* Optimize the access just a bit. */
- if (GET_CODE (dst) == MEM
- && MEM_ALIGN (dst) >= GET_MODE_ALIGNMENT (mode)
+ if (GET_CODE (dest) == MEM
+ && MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode)
&& bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0
&& bytelen == GET_MODE_SIZE (mode))
- emit_move_insn (adjust_address (dst, mode, bytepos), tmps[i]);
+ emit_move_insn (adjust_address (dest, mode, bytepos), tmps[i]);
else
- store_bit_field (dst, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,
+ store_bit_field (dest, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT,
mode, tmps[i], ssize);
}
--- /dev/null
+// PR target/6043
+// This testcase ICEd on IA-64 because emit_group_store
+// did not handle loading CONCAT from register group
+// { dg-do compile }
+
+struct C
+{
+ C (double y, double z) { __real__ x = y; __imag__ x = z; }
+ double r () const { return __real__ x; }
+ double i () const { return __imag__ x; }
+ __complex__ double x;
+};
+
+inline C conj (const C& x)
+{
+ return C (x.r (), - x.i ());
+}
+
+void foo (void)
+{
+ C x (1.0, 1.0);
+ conj (x);
+}