arm: Add earlyclobber to MVE instructions that require it
authorAndre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
Mon, 23 Mar 2020 17:23:25 +0000 (17:23 +0000)
committerAndre Vieira <andre.simoesdiasvieira@arm.com>
Mon, 23 Mar 2020 17:45:26 +0000 (17:45 +0000)
This patch adds an earlyclobber to the MVE instructions that require it and were
missing it. These are vrev64 and 32-bit element variants of vcadd, vhcadd vcmul,
vmull[bt] and vqdmull[bt].

gcc/ChangeLog:
2020-03-23  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* config/arm/mve.md (earlyclobber_32): New mode attribute.
(mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.

gcc/ChangeLog
gcc/config/arm/mve.md

index 8804b0c5249cef1d4665a81a807b1122ed40e721..fcd34fd8fae68e9635be77047a1951da77b4d9d0 100644 (file)
@@ -1,3 +1,9 @@
+2020-03-23  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * config/arm/mve.md (earlyclobber_32): New mode attribute.
+       (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
+        mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
+
 2020-03-23  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/94261
index 2e28d9d8408127dd52b9d16c772e7f27a47d390a..699290e77002201fd0235309bc5f678d96e79cac 100644 (file)
 (define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
 (define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI  "h") (V4SI "w") (V8HF "h")
                              (V4SF "w")])
+(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
+                                               (V8HF "=w") (V4SF "=&w")])
 
 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
 (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
 ;;
 (define_insn "mve_vrev64q_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
         VREV64Q_F))
   ]
 ;;
 (define_insn "mve_vrev64q_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
         VREV64Q))
   ]
 ;;
 (define_insn "mve_vcaddq_rot270_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
                       (match_operand:MVE_2 2 "s_register_operand" "w")]
         VCADDQ_ROT270))
 ;;
 (define_insn "mve_vcaddq_rot90_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
                       (match_operand:MVE_2 2 "s_register_operand" "w")]
         VCADDQ_ROT90))
 ;;
 (define_insn "mve_vhcaddq_rot270_s<mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
                       (match_operand:MVE_2 2 "s_register_operand" "w")]
         VHCADDQ_ROT270_S))
 ;;
 (define_insn "mve_vhcaddq_rot90_s<mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
                       (match_operand:MVE_2 2 "s_register_operand" "w")]
         VHCADDQ_ROT90_S))
 ;;
 (define_insn "mve_vmullbq_int_<supf><mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
                                  (match_operand:MVE_2 2 "s_register_operand" "w")]
         VMULLBQ_INT))
 ;;
 (define_insn "mve_vmulltq_int_<supf><mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
                                  (match_operand:MVE_2 2 "s_register_operand" "w")]
         VMULLTQ_INT))
 ;;
 (define_insn "mve_vcaddq_rot270_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
                       (match_operand:MVE_0 2 "s_register_operand" "w")]
         VCADDQ_ROT270_F))
 ;;
 (define_insn "mve_vcaddq_rot90_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
                       (match_operand:MVE_0 2 "s_register_operand" "w")]
         VCADDQ_ROT90_F))
 ;;
 (define_insn "mve_vcmulq_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
                       (match_operand:MVE_0 2 "s_register_operand" "w")]
         VCMULQ_F))
 ;;
 (define_insn "mve_vcmulq_rot180_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
                       (match_operand:MVE_0 2 "s_register_operand" "w")]
         VCMULQ_ROT180_F))
 ;;
 (define_insn "mve_vcmulq_rot270_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
                       (match_operand:MVE_0 2 "s_register_operand" "w")]
         VCMULQ_ROT270_F))
 ;;
 (define_insn "mve_vcmulq_rot90_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
                       (match_operand:MVE_0 2 "s_register_operand" "w")]
         VCMULQ_ROT90_F))
 ;;
 (define_insn "mve_vqdmullbq_n_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
                                  (match_operand:<V_elem> 2 "s_register_operand" "r")]
         VQDMULLBQ_N_S))
 ;;
 (define_insn "mve_vqdmullbq_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
         VQDMULLBQ_S))
 ;;
 (define_insn "mve_vqdmulltq_n_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
                                  (match_operand:<V_elem> 2 "s_register_operand" "r")]
         VQDMULLTQ_N_S))
 ;;
 (define_insn "mve_vqdmulltq_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
         VQDMULLTQ_S))
 ;;
 (define_insn "mve_vcaddq_rot270_m_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
                       (match_operand:MVE_2 2 "s_register_operand" "w")
                       (match_operand:MVE_2 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcaddq_rot90_m_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
                       (match_operand:MVE_2 2 "s_register_operand" "w")
                       (match_operand:MVE_2 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vmullbq_int_m_<supf><mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                                  (match_operand:MVE_2 2 "s_register_operand" "w")
                                  (match_operand:MVE_2 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vmulltq_int_m_<supf><mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                                  (match_operand:MVE_2 2 "s_register_operand" "w")
                                  (match_operand:MVE_2 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vhcaddq_rot270_m_s<mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
                       (match_operand:MVE_2 2 "s_register_operand" "w")
                       (match_operand:MVE_2 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vhcaddq_rot90_m_s<mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
                       (match_operand:MVE_2 2 "s_register_operand" "w")
                       (match_operand:MVE_2 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vqdmullbq_m_n_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:<V_elem> 3 "s_register_operand" "r")
 ;;
 (define_insn "mve_vqdmullbq_m_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:MVE_5 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vqdmulltq_m_n_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:<V_elem> 3 "s_register_operand" "r")
 ;;
 (define_insn "mve_vqdmulltq_m_s<mode>"
   [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:MVE_5 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcaddq_rot270_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:MVE_0 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcaddq_rot90_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:MVE_0 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcmulq_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:MVE_0 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcmulq_rot180_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:MVE_0 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcmulq_rot270_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:MVE_0 3 "s_register_operand" "w")
 ;;
 (define_insn "mve_vcmulq_rot90_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:MVE_0 3 "s_register_operand" "w")