fix fmvis decoder, it's now a 2-operand instruction

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 64bde71f7e12f9eae9dfddf2013814fe441a2b5f..665ea51298281413dc4ca8a4bd5f0bdf3b02b3e5 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -210,7 +210,7 @@ Special Registers Altered:
 
 X-Form
 
-* fmvis FRS,FRS,SI
+* fmvis FRS,SI
 
 Pseudo-code:
 

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 735f9f37935a3893dfe9cb890fd330ecc20daa4c..1a39f0914755322b498c398f9ce3bb30087b1fbb 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -339,14 +339,14 @@ def fmvis(fields):
     # | PO   |   FRS         |     d1      |      d0     |   XO |d2  |
     PO = 22
     XO = 0b000011
-    (FRS, d0, d1, d2) = fields
+    Rc = 0
+    (FRS, imm) = fields
     return instruction(
         (PO , 0 , 5),
         (FRS, 6 , 10),
-        (d0 , 11, 15),
-        (d1 , 16, 26),
+        (imm, 11, 26),
         (XO , 27, 30),
-        (d2 , 31, 31),
+        (Rc , 31, 31),
     )
 
 
@@ -357,7 +357,6 @@ for (name, hook) in (
             ("fsins", fsins),
             ("fcoss", fcoss),
             ("ternlogi", ternlogi),
-            ("fmvis", fmvis)
         ):
     CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)
     CUSTOM_INSNS[f"{name}."] = functools.partial(hook, Rc=True)
@@ -365,6 +364,7 @@ CUSTOM_INSNS["bmask"] = bmask
 CUSTOM_INSNS["svshape"] = svshape
 CUSTOM_INSNS["svindex"] = svindex
 CUSTOM_INSNS["svremap"] = svremap
+CUSTOM_INSNS["fmvis"] = fmvis
 
 for (name, imm, wide) in (
             ("grev", False, False),
@@ -388,7 +388,6 @@ for (name, XO) in (
             ("absdacu", 0b1111110110),
             ("absdacs", 0b0111110110),
             ("cprop"  , 0b0110001110),
-            ("fmvis"  , 0b0000000011),
         ):
     CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)
     CUSTOM_INSNS[f"{name}."] = functools.partial(av, XO=XO, Rc=True)

diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
index 3e057e4f214dbefe35c59469a03022414a14b255..26d9692b99b6e90b8ab1fdc1aa79fc5ba9556d21 100644 (file)
--- a/src/openpower/test/alu/fmvis_cases.py
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -13,9 +13,9 @@ import unittest
 class FMVISTestCase(TestAccumulatorBase):
 
     def case_0_fmvis(self):
-        lst = SVP64Asm(["fmvis 5, 5, 0x4000",
-                        "fmvis 6, 6, 0x2122",
-                        "fmvis 7, 7, 0x3E80",
+        lst = SVP64Asm(["fmvis 5, 0x4000",
+                        "fmvis 6, 0x2122",
+                        "fmvis 7, 0x3E80",
                        ])
         lst = list(lst)