i965: Fix varying payload reg assignment for the non-GLSL-instructions path.

I don't have a testcase for this, but it seems clearly wrong.
(cherry picked from commit dc657f3929fbe03275b3fae4ef84f02e74b51114)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 08cac730c2981f8d9e2f64fd1c7618af4b1ad5a3..6faea018fbcddfa09c354c14845bd2848aa26a61 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,7 +69,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
  */
 static void init_registers( struct brw_wm_compile *c )
 {
-   struct brw_context *brw = c->func.brw;
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -85,15 +84,18 @@ static void init_registers( struct brw_wm_compile *c )
 
    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
       if (c->key.vp_outputs_written & (1<<j)) {
-        /* index for vs output and ps input are not the same 
-           in shader varying */
-        GLuint index;
-        if (j > FRAG_ATTRIB_VAR0)
-            index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+        int fp_index;
+
+        if (j >= VERT_RESULT_VAR0)
+           fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+        else if (j <= VERT_RESULT_TEX7)
+           fp_index = j;
         else
-            index = j;
+           fp_index = -1;
+
         nr_interp_regs++;
-        prealloc_reg(c, &c->payload.input_interp[index], i++);
+        if (fp_index >= 0)
+           prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
       }
    }