Custom step to add global clock buffers

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index 3f3394c9647787fda40f5d63e6512f32a9eb725e..82dfa3cd8862a82a01d7da3f9a39edbd56f71d06 100644 (file)
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -1,5 +1,6 @@
 
 OBJS += techlibs/efinix/synth_efinix.o
+OBJS += techlibs/efinix/efinix_gbuf.o
 
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))

diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index aaff955a274e61beecf6b8bde3e208dc06a714cc..2cbf8ae4bcc12a916f531dd53ba646e5bac81d16 100644 (file)
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -33,4 +33,12 @@ module EFX_FF(
    parameter SR_VALUE = 0;
    parameter SR_SYNC_PRIORITY = 0;
    parameter D_POLARITY = 1;
-endmodule
\ No newline at end of file
+endmodule
+
+module EFX_GBUFCE (
+   input CE,
+   input I,
+   output O
+);
+   parameter CE_POLARITY = 1'b1;
+endmodule

diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc
new file mode 100644 (file)
index 0000000..50f84c3
--- /dev/null
+++ b/techlibs/efinix/efinix_gbuf.cc
@@ -0,0 +1,113 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void handle_gbufs(Module *module)
+{
+       SigMap sigmap(module);
+
+       pool<SigBit> clk_bits;
+       dict<SigBit, SigBit> rewrite_bits;
+       vector<pair<Cell*, SigBit>> pad_bits;
+
+       for (auto cell : module->cells())
+       {
+               if (cell->type == "\\EFX_FF") {
+                       for (auto bit : sigmap(cell->getPort("\\CLK")))
+                               clk_bits.insert(bit);
+               }
+       }
+
+       for (auto wire : vector<Wire*>(module->wires()))
+       {
+               if (!wire->port_input)
+                       continue;
+
+               for (int index = 0; index < GetSize(wire); index++)
+               {
+                       SigBit bit(wire, index);
+                       SigBit canonical_bit = sigmap(bit);
+
+                       if (!clk_bits.count(canonical_bit))
+                               continue;
+
+                       Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
+                       SigBit new_bit = module->addWire(NEW_ID);
+                       c->setParam("\\CE_POLARITY", State::S1);
+                       c->setPort("\\O", new_bit);
+                       c->setPort("\\CE", State::S1);
+                       pad_bits.push_back(make_pair(c, bit));
+                       rewrite_bits[canonical_bit] = new_bit;
+
+                       log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
+               }
+       }
+
+       auto rewrite_function = [&](SigSpec &s) {
+               for (auto &bit : s) {
+                       SigBit canonical_bit = sigmap(bit);
+                       if (rewrite_bits.count(canonical_bit))
+                               bit = rewrite_bits.at(canonical_bit);
+               }
+       };
+
+       module->rewrite_sigspecs(rewrite_function);
+
+       for (auto &it : pad_bits)
+               it.first->setPort("\\I", it.second);
+}
+
+struct EfinixGbufPass : public Pass {
+       EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
+       void help() YS_OVERRIDE
+       {
+               //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+               log("\n");
+               log("    efinix_gbuf [options] [selection]\n");
+               log("\n");
+               log("Add Efinix global clock buffers to top module as needed.\n");
+               log("\n");
+       }
+       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       {
+               log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
+               
+               size_t argidx;
+               for (argidx = 1; argidx < args.size(); argidx++)
+               {
+                       break;
+               }
+               extra_args(args, argidx, design);
+
+               Module *module = design->top_module();
+
+               if (module == nullptr)
+                       log_cmd_error("No top module found.\n");
+
+               handle_gbufs(module);           
+       }
+} EfinixGbufPass;
+
+PRIVATE_NAMESPACE_END

diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 9c644d3638b220edeb2f580d18f80ab8f3e1a6e2..3f17bafa3a6056840396fe911a06d3f3d3d86209 100644 (file)
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -181,6 +181,12 @@ struct SynthEfinixPass : public ScriptPass
                        run("clean");
                }
 
+               if (check_label("map_gbuf"))
+               {
+                       run("efinix_gbuf");
+                       run("clean");
+               }
+               
                if (check_label("check"))
                {
                        run("hierarchy -check");