Rename LiteDRAM to gram

diff --git a/gram/common.py b/gram/common.py
index d416d16c04269fbc9a7f319cddd63d9c5e6d455e..ab2a485040f43db87ff1bb3a74a97b3e385973ff 100644 (file)
--- a/gram/common.py
+++ b/gram/common.py
@@ -314,12 +314,12 @@ class gramNativePort(Settings):
 
 class gramNativeWritePort(gramNativePort):
     def __init__(self, *args, **kwargs):
-        LiteDRAMNativePort.__init__(self, "write", *args, **kwargs)
+        gramNativePort.__init__(self, "write", *args, **kwargs)
 
 
 class gramNativeReadPort(gramNativePort):
     def __init__(self, *args, **kwargs):
-        LiteDRAMNativePort.__init__(self, "read", *args, **kwargs)
+        gramNativePort.__init__(self, "read", *args, **kwargs)
 
 
 # Timing Controllers -------------------------------------------------------------------------------