i965: enable the emission of the DIM instruction
authorSamuel Iglesias Gonsálvez <siglesias@igalia.com>
Thu, 7 Jul 2016 06:38:22 +0000 (08:38 +0200)
committerSamuel Iglesias Gonsálvez <siglesias@igalia.com>
Thu, 14 Jul 2016 06:06:01 +0000 (08:06 +0200)
v2 (Matt):
- Take a DF source argument for the DIM instruction emission
in the visitors.
- Indentation.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_eu.c
src/mesa/drivers/dri/i965/brw_eu.h
src/mesa/drivers/dri/i965/brw_eu_emit.c
src/mesa/drivers/dri/i965/brw_fs_builder.h
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
src/mesa/drivers/dri/i965/brw_vec4.h
src/mesa/drivers/dri/i965/brw_vec4_builder.h
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

index d2cd53a2fc20c4024307b3bc409c529f6d79cece..740d03dc963c3c461bac2a51af5974ebbe31e9c9 100644 (file)
@@ -857,7 +857,7 @@ enum opcode {
    BRW_OPCODE_XOR =    7,
    BRW_OPCODE_SHR =    8,
    BRW_OPCODE_SHL =    9,
-   // BRW_OPCODE_DIM = 10,  /**< Gen7.5 only */ /* Reused */
+   BRW_OPCODE_DIM =    10,  /**< Gen7.5 only */ /* Reused */
    // BRW_OPCODE_SMOV =        10,  /**< Gen8+       */ /* Reused */
    /* Reserved - 11 */
    BRW_OPCODE_ASR =    12,
index cc252de1cd6be39f21868097352b8b167f14c902..3a309dce8faeb2dbe7d90dac501e657422b3fe07 100644 (file)
@@ -421,7 +421,7 @@ enum gen {
 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 
 static const struct opcode_desc opcode_10_descs[] = {
-   { .name = "dim",   .nsrc = 0, .ndst = 0, .gens = GEN75 },
+   { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
    { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 };
 
index b057f179917e511ddaaaa192130e2b00f159155b..09f51dbffbd0c5747dae336707658b59d4ddc01d 100644 (file)
@@ -157,6 +157,7 @@ ALU2(OR)
 ALU2(XOR)
 ALU2(SHR)
 ALU2(SHL)
+ALU1(DIM)
 ALU2(ASR)
 ALU1(F32TO16)
 ALU1(F16TO32)
index 2a8e66149d310ce699f94e2a3ff899f21727348e..f2f554101ad24b93442f36951c9f16ef19c8db14 100644 (file)
@@ -1064,6 +1064,7 @@ ALU2(OR)
 ALU2(XOR)
 ALU2(SHR)
 ALU2(SHL)
+ALU1(DIM)
 ALU2(ASR)
 ALU1(FRC)
 ALU1(RNDD)
index f22903e523405ae5d291078448554eb30f5ceea0..8e434844ddb3b1e7318c4dc62cf0d658fcd18fb6 100644 (file)
@@ -460,6 +460,7 @@ namespace brw {
       ALU1(CBIT)
       ALU2(CMPN)
       ALU3(CSEL)
+      ALU1(DIM)
       ALU2(DP2)
       ALU2(DP3)
       ALU2(DP4)
index ce1ec0a588561b533fb831dbaa183434caf8e02d..1e9c7da9e278a203d9c1fa6082d4b05f2d627017 100644 (file)
@@ -2082,6 +2082,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
         generate_barrier(inst, src[0]);
         break;
 
+      case BRW_OPCODE_DIM:
+         assert(devinfo->is_haswell);
+         assert(src[0].type == BRW_REGISTER_TYPE_DF);
+         assert(dst.type == BRW_REGISTER_TYPE_DF);
+         brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
+         break;
+
       default:
          unreachable("Unsupported opcode");
 
index 76dea04ea01cf5a7f81217c0d6007361572e9636..3043147b18731429655c7ff0502ca4b4feaa9617 100644 (file)
@@ -213,6 +213,8 @@ public:
    EMIT3(MAD)
    EMIT2(ADDC)
    EMIT2(SUBB)
+   EMIT1(DIM)
+
 #undef EMIT1
 #undef EMIT2
 #undef EMIT3
index 3a8617e05acf61409a7169c713722eb1a71f2acf..d25a87a81c0db79eafa5f104dc93e831504c0561 100644 (file)
@@ -373,6 +373,7 @@ namespace brw {
       ALU1(CBIT)
       ALU2(CMPN)
       ALU3(CSEL)
+      ALU1(DIM)
       ALU2(DP2)
       ALU2(DP3)
       ALU2(DP4)
index bb0254ee51ec0c153880b6fc4ffd2857ff43b721..3878c4ad268bede23a12da401a377510e30c922f 100644 (file)
@@ -2014,6 +2014,13 @@ generate_code(struct brw_codegen *p,
          generate_mov_indirect(p, inst, dst, src[0], src[1], src[2]);
          break;
 
+      case BRW_OPCODE_DIM:
+         assert(devinfo->is_haswell);
+         assert(src[0].type == BRW_REGISTER_TYPE_DF);
+         assert(dst.type == BRW_REGISTER_TYPE_DF);
+         brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
+         break;
+
       default:
          unreachable("Unsupported opcode");
       }
index b392919e540c0563802868e3dd91ff5ee1a26c55..652b4530c56021230176c250520f7016c019c415 100644 (file)
@@ -183,6 +183,7 @@ ALU3(MAD)
 ALU2_ACC(ADDC)
 ALU2_ACC(SUBB)
 ALU2(MAC)
+ALU1(DIM)
 
 /** Gen4 predicated IF. */
 vec4_instruction *