BRW_OPCODE_XOR = 7,
BRW_OPCODE_SHR = 8,
BRW_OPCODE_SHL = 9,
- // BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
+ BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
// BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
/* Reserved - 11 */
BRW_OPCODE_ASR = 12,
#define GEN_LE(gen) (GEN_LT(gen) | (gen))
static const struct opcode_desc opcode_10_descs[] = {
- { .name = "dim", .nsrc = 0, .ndst = 0, .gens = GEN75 },
+ { .name = "dim", .nsrc = 1, .ndst = 1, .gens = GEN75 },
{ .name = "smov", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
};
ALU2(XOR)
ALU2(SHR)
ALU2(SHL)
+ALU1(DIM)
ALU2(ASR)
ALU1(F32TO16)
ALU1(F16TO32)
ALU2(XOR)
ALU2(SHR)
ALU2(SHL)
+ALU1(DIM)
ALU2(ASR)
ALU1(FRC)
ALU1(RNDD)
ALU1(CBIT)
ALU2(CMPN)
ALU3(CSEL)
+ ALU1(DIM)
ALU2(DP2)
ALU2(DP3)
ALU2(DP4)
generate_barrier(inst, src[0]);
break;
+ case BRW_OPCODE_DIM:
+ assert(devinfo->is_haswell);
+ assert(src[0].type == BRW_REGISTER_TYPE_DF);
+ assert(dst.type == BRW_REGISTER_TYPE_DF);
+ brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
+ break;
+
default:
unreachable("Unsupported opcode");
EMIT3(MAD)
EMIT2(ADDC)
EMIT2(SUBB)
+ EMIT1(DIM)
+
#undef EMIT1
#undef EMIT2
#undef EMIT3
ALU1(CBIT)
ALU2(CMPN)
ALU3(CSEL)
+ ALU1(DIM)
ALU2(DP2)
ALU2(DP3)
ALU2(DP4)
generate_mov_indirect(p, inst, dst, src[0], src[1], src[2]);
break;
+ case BRW_OPCODE_DIM:
+ assert(devinfo->is_haswell);
+ assert(src[0].type == BRW_REGISTER_TYPE_DF);
+ assert(dst.type == BRW_REGISTER_TYPE_DF);
+ brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
+ break;
+
default:
unreachable("Unsupported opcode");
}
ALU2_ACC(ADDC)
ALU2_ACC(SUBB)
ALU2(MAC)
+ALU1(DIM)
/** Gen4 predicated IF. */
vec4_instruction *