litesata: adapt to new SoC API

diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
index 8f4b512627e5e99ab8074236fe7d4681fa247764..c8f67b3d2ad960da387c2441f35772b44d732265 100755 (executable)
--- a/misoclib/mem/litesata/example_designs/make.py
+++ b/misoclib/mem/litesata/example_designs/make.py
@@ -124,7 +124,7 @@ BIST: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.csr_regions)
+               csr_csv = cpuif.get_csr_csv(soc.get_csr_regions())
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-core"]:

diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py
index 63f1d338e7cb720403ed132449a766173211603e..038f8532d61e63b5501c3428af8d2ee11213b832 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/bist.py
+++ b/misoclib/mem/litesata/example_designs/targets/bist.py
@@ -89,14 +89,15 @@ class BISTSoC(SoC, AutoCSR):
        csr_map.update(SoC.csr_map)
        def __init__(self, platform):
                clk_freq = 166*1000000
-               self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
-               SoC.__init__(self, platform, clk_freq, self.uart2wb,
-                       with_cpu=False,
+               SoC.__init__(self, platform, clk_freq,
+                       cpu_type="none",
                        with_csr=True, csr_data_width=32,
                        with_uart=False,
                        with_identifier=True,
                        with_timer=False
                )
+               self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
+               self.add_wb_master(self.cpu_or_bridge.wishbone)
                self.submodules.crg = _CRG(platform)
 
                # SATA PHY/Core/Frontend