sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings

req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings

diff --git a/misoclib/mem/sdram/__init__.py b/misoclib/mem/sdram/__init__.py
index f861d63ccdcaf07961cb4863835db15ea5f46c3f..00acf678f73a939f55c4f922c73976cf3df716be 100644 (file)
--- a/misoclib/mem/sdram/__init__.py
+++ b/misoclib/mem/sdram/__init__.py
@@ -8,5 +8,6 @@ GeomSettingsT = namedtuple("_GeomSettings", "bank_a row_a col_a mux_a")
 def GeomSettings(bank_a, row_a, col_a):
        return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a))
 
-TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \
-       " req_queue_size read_time write_time")
+TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
+
+ControllerSettings = namedtuple("ControllerSettings", "req_queue_size read_time write_time")

diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py
index f31277528a3c339c36aa04f464fda12ee951ac74..b01149479b596b3ddb57cc79af3bf0bb201dae43 100644 (file)
--- a/misoclib/mem/sdram/core/__init__.py
+++ b/misoclib/mem/sdram/core/__init__.py
@@ -7,22 +7,23 @@ from misoclib.mem.sdram.core import minicon, lasmicon
 from misoclib.mem.sdram.core import lasmixbar
 
 class SDRAMCore(Module, AutoCSR):
-       def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs):
+       def __init__(self, phy, ramcon_type, geom_settings, timing_settings, controller_settings, **kwargs):
                # DFI
-               self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
+               self.submodules.dfii = dfii.DFIInjector(geom_settings.mux_a, geom_settings.bank_a,
                                phy.settings.dfi_d, phy.settings.nphases)
                self.comb += Record.connect(self.dfii.master, phy.dfi)
 
                # LASMICON
                if ramcon_type == "lasmicon":
-                       self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, sdram_geom, sdram_timing, **kwargs)
+                       self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings,
+                               controller_settings, **kwargs)
                        self.comb += Record.connect(controller.dfi, self.dfii.slave)
 
                        self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
 
                # MINICON
                elif ramcon_type == "minicon":
-                       self.submodules.controller = controller = minicon.Minicon(phy.settings, sdram_geom, sdram_timing)
+                       self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings)
                        self.comb += Record.connect(controller.dfi, self.dfii.slave)
                else:
                        raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))

diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py
index 393e218b320b7ac1aa68a816fd9e4fbfcdf25e95..5d213dd1da25e8e0b3e091a122176ce402686dca 100644 (file)
--- a/misoclib/mem/sdram/core/lasmicon/__init__.py
+++ b/misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -7,7 +7,7 @@ from misoclib.mem.sdram.core.lasmicon.bankmachine import *
 from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 
 class LASMIcon(Module):
-       def __init__(self, phy_settings, geom_settings, timing_settings, **kwargs):
+       def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
                if phy_settings.memtype in ["SDR"]:
                        burst_length = phy_settings.nphases*1 # command multiplication*SDR
                elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
@@ -22,7 +22,7 @@ class LASMIcon(Module):
                        aw=geom_settings.row_a + geom_settings.col_a - address_align,
                        dw=phy_settings.dfi_d*phy_settings.nphases,
                        nbanks=2**geom_settings.bank_a,
-                       req_queue_size=timing_settings.req_queue_size,
+                       req_queue_size=controller_settings.req_queue_size,
                        read_latency=phy_settings.read_latency+1,
                        write_latency=phy_settings.write_latency+1)
                self.nrowbits = geom_settings.col_a - address_align
@@ -31,10 +31,10 @@ class LASMIcon(Module):
 
                self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a,
                        timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
-               self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i,
+               self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
                                getattr(self.lasmic, "bank"+str(i)))
                        for i in range(2**geom_settings.bank_a)]
-               self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings,
+               self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings,
                        self.bank_machines, self.refresher,
                        self.dfi, self.lasmic,
                        **kwargs)

diff --git a/misoclib/mem/sdram/core/lasmicon/bankmachine.py b/misoclib/mem/sdram/core/lasmicon/bankmachine.py
index 3397bb36f50c192edc889a346409bfd49f1cab6d..bb1d9c76e9f010c7bf944e5a0b0588568639e0b1 100644 (file)
--- a/misoclib/mem/sdram/core/lasmicon/bankmachine.py
+++ b/misoclib/mem/sdram/core/lasmicon/bankmachine.py
@@ -26,7 +26,7 @@ class _AddressSlicer:
                        return Cat(Replicate(0, self.address_align), address[:split])
 
 class BankMachine(Module):
-       def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
+       def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req):
                self.refresh_req = Signal()
                self.refresh_gnt = Signal()
                self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a)
@@ -34,7 +34,7 @@ class BankMachine(Module):
                ###
 
                # Request FIFO
-               self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size)
+               self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], controller_settings.req_queue_size)
                self.comb += [
                        self.req_fifo.din.we.eq(req.we),
                        self.req_fifo.din.adr.eq(req.adr),

diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/core/lasmicon/multiplexer.py
index fe47e7c9a41f460a7c1168ad83e0057128893ad3..db24e633b234532de32025f1d3ef8de05625a694 100644 (file)
--- a/misoclib/mem/sdram/core/lasmicon/multiplexer.py
+++ b/misoclib/mem/sdram/core/lasmicon/multiplexer.py
@@ -89,7 +89,7 @@ class _Steerer(Module):
                        ]
 
 class Multiplexer(Module, AutoCSR):
-       def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic,
+       def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic,
                        with_bandwidth=False):
                assert(phy_settings.nphases == len(dfi.phases))
 
@@ -137,8 +137,8 @@ class Multiplexer(Module, AutoCSR):
                        else:
                                self.comb += max_time.eq(0)
                        return en, max_time
-               read_time_en, max_read_time = anti_starvation(timing_settings.read_time)
-               write_time_en, max_write_time = anti_starvation(timing_settings.write_time)
+               read_time_en, max_read_time = anti_starvation(controller_settings.read_time)
+               write_time_en, max_write_time = anti_starvation(controller_settings.write_time)
 
                # Refresh
                self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 237cad227b55c4e641c85c53acd27a5421129d0d..82725b65b50be9c69a613aa10234174e25a6c8f6 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -32,7 +32,7 @@ class SDRAMSoC(SoC):
 
                self._sdram_phy_registered = False
 
-       def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
+       def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_settings):
                if self._sdram_phy_registered:
                        raise FinalizeError
                self._sdram_phy_registered = True
@@ -40,7 +40,7 @@ class SDRAMSoC(SoC):
                        raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
 
                # Core
-               self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, sdram_geom, sdram_timing)
+               self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, geom_settings, timing_settings, controller_settings)
 
                # LASMICON frontend
                if self.ramcon_type == "lasmicon":
@@ -68,7 +68,7 @@ class SDRAMSoC(SoC):
                # MINICON frontend
                elif self.ramcon_type == "minicon":
                        sdram_width = flen(self.sdram.controller.bus.dat_r)
-                       main_ram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
+                       main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8
 
                        if sdram_width == 32:
                                self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)

diff --git a/targets/de0nano.py b/targets/de0nano.py
index 769613ea07c73e359f1fa4f90da7b86840936262..c1be8d68f90c8dc8d9b7e0ca940a61a51bb8f07f 100644 (file)
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -90,26 +90,27 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform)
 
                if not self.with_main_ram:
-                       sdram_geom = sdram.GeomSettings(
+                       sdram_geom_settings = sdram.GeomSettings(
                                bank_a=2,
                                row_a=13,
                                col_a=9
                        )
 
-                       sdram_timing = sdram.TimingSettings(
+                       sdram_timing_settings = sdram.TimingSettings(
                                tRP=self.ns(20),
                                tRCD=self.ns(20),
                                tWR=self.ns(20),
                                tWTR=2,
                                tREFI=self.ns(7800, False),
-                               tRFC=self.ns(70),
-
+                               tRFC=self.ns(70)
+                       )
+                       sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
-
                        self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
+                       self.register_sdram_phy(self.sdrphy, sdram_geom_settings, sdram_timing_settings,
+                               sdram_controller_settings)
 
 default_subtarget = BaseSoC

diff --git a/targets/kc705.py b/targets/kc705.py
index 75079483af9375d8c7622842a3d50a1e28f8f57b..0006e50006550bc06f6fd729c9baf14416967887 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -83,25 +83,27 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform)
 
                if not self.with_main_ram:
-                       sdram_geom = sdram.GeomSettings(
+                       sdram_geom_settings = sdram.GeomSettings(
                                bank_a=3,
                                row_a=16,
                                col_a=10
                        )
-                       sdram_timing = sdram.TimingSettings(
+                       sdram_timing_settings = sdram.TimingSettings(
                                tRP=self.ns(15),
                                tRCD=self.ns(15),
                                tWR=self.ns(15),
                                tWTR=2,
                                tREFI=self.ns(7800, False),
-                               tRFC=self.ns(70),
-
+                               tRFC=self.ns(70)
+                       )
+                       sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
                        self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
-                       self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
+                       self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+                               sdram_controller_settings)
 
                spiflash_pads = platform.request("spiflash")
                spiflash_pads.clk = Signal()

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 0278b342e9dccbfc02757c9b2c2479045a68b12d..54943497b7ea36a7063388b4eda58ec800431202 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -41,26 +41,28 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
                if not self.with_main_ram:
-                       sdram_geom = sdram.GeomSettings(
+                       sdram_geom_settings = sdram.GeomSettings(
                                bank_a=2,
                                row_a=13,
                                col_a=10
                        )
-                       sdram_timing = sdram.TimingSettings(
+                       sdram_timing_settings = sdram.TimingSettings(
                                tRP=self.ns(15),
                                tRCD=self.ns(15),
                                tWR=self.ns(15),
                                tWTR=2,
                                tREFI=self.ns(7800, False),
                                tRFC=self.ns(70),
-
+                       )
+                       sdram_controller_settings =  sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
                        self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
                                rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
-                       self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
+                       self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+                               sdram_controller_settings)
 
 
                        self.comb += [

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 3bab29a421e8795f722d6f31585596ed0092802c..57b4f9c17a161fd39d1379516d6f33a3de15ec69 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -98,18 +98,20 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform, clk_freq)
 
                if not self.with_main_ram:
-                       sdram_geom = sdram.GeomSettings(
+                       sdram_geom_settings = sdram.GeomSettings(
                                bank_a=2,
                                row_a=13,
                                col_a=10
                        )
-                       sdram_timing = sdram.TimingSettings(
+                       sdram_timing_settings = sdram.TimingSettings(
                                tRP=self.ns(15),
                                tRCD=self.ns(15),
                                tWR=self.ns(15),
                                tWTR=2,
                                tREFI=self.ns(64*1000*1000/8192, False),
-                               tRFC=self.ns(72),
+                               tRFC=self.ns(72)
+                       )
+                       sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
@@ -123,7 +125,8 @@ class BaseSoC(SDRAMSoC):
                        platform.add_platform_command("""
        PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
        """)
-                       self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
+                       self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+                               sdram_controller_settings)
 
                self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
                # If not in ROM, BIOS is in SPI flash

diff --git a/targets/ppro.py b/targets/ppro.py
index c50e9bb48b8434aa4c3df2b0e274ddfa00b2bfd3..ffd83195b55171ae7cacf7e09d200a1018da2c77 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -74,24 +74,27 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform, clk_freq)
 
                if not self.with_main_ram:
-                       sdram_geom = sdram.GeomSettings(
+                       sdram_geom_settings = sdram.GeomSettings(
                                bank_a=2,
                                row_a=12,
                                col_a=8
                        )
-                       sdram_timing = sdram.TimingSettings(
+                       sdram_timing_settings = sdram.TimingSettings(
                                tRP=self.ns(15),
                                tRCD=self.ns(15),
                                tWR=self.ns(14),
                                tWTR=2,
                                tREFI=self.ns(64*1000*1000/4096, False),
-                               tRFC=self.ns(66),
+                               tRFC=self.ns(66)
+                       )
+                       sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
                        self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
+                       self.register_sdram_phy(self.sdrphy, sdram_geom_settings, sdram_timing_settings,
+                               sdram_controller_settings)
 
                self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
                self.flash_boot_address = 0x70000