pipistrello: fix FPGA speed grade

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 127f609c6d3f280bfeafe74318b7cd5ca6e549d5..08c1482753c4b4ab74b1c86979fbb7c7367f3e29 100644 (file)
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
@@ -130,7 +130,7 @@ class Platform(XilinxPlatform):
     default_clk_period = 20
 
     def __init__(self):
-        XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
+        XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
         self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
 
     def create_programmer(self):