-2011-05-31 Dodji Seketeli <dodji@redhat.com>
-
- PR debug/49047
- * dwarf2out.c (gen_subprogram_die): Emit linkage name attribute
- for concrete functions containing the code of cloned functions.
-
2011-05-31 Richard Guenther <rguenther@suse.de>
* tree-ssa-forwprop.c (forward_propagate_into_comparison): Rename
subr_die = new_die (DW_TAG_subprogram, context_die, decl);
add_abstract_origin_attribute (subr_die, origin);
- /* This is where the actual code for a cloned function is.
- Let's emit linkage name attribute for it. This helps
- debuggers to e.g, set breakpoints into
- constructors/destructors when the user asks "break
- K::K". */
- add_linkage_name (subr_die, decl);
}
else if (old_die)
{
-2011-05-31 Dodji Seketeli <dodji@redhat.com>
-
- PR debug/49047
- * g++.dg/debug/dwarf2/cdtor-1.C: New test.
-
2011-05-31 Ira Rosen <ira.rosen@linaro.org>
PR testsuite/49239
+++ /dev/null
-// origin PR debug/49047
-// { dg-options "-g -dA" }
-// { dg-do compile }
-
-struct K
-{
- K () { }
- ~K () { }
-};
-
-int
-main()
-{
- K k;
-}
-
-// { dg-final {scan-assembler-times "\[^\n\r\]*DW_AT_MIPS_linkage_name:" 2 } }
-2011-05-31 H.J. Lu <hongjiu.lu@intel.com>
-
- PR libgcj/49193
- * configure.host (sysdeps_dir): Set to i386 for x86_64.
-
- * sysdep/i386/locks.h (compare_and_swap): Call
- __sync_bool_compare_and_swap.
- (release_set): Call write_barrier ().
-
- * sysdep/x86-64/locks.h: Removed.
-
2011-04-24 Gerald Pfeifer <gerald@pfeifer.com>
* README: Refer to our generic bug reporting page.
slow_pthread_self=yes
;;
x86_64-*)
- sysdeps_dir=i386
+ sysdeps_dir=x86-64
# For 64-bit we always use SSE registers for arithmetic,
# which doesn't have the extra precision problems of the fpu.
# But be careful about 32-bit multilibs.
slow_pthread_self=
;;
i[34567]86-*-solaris2.1[0-9]* )
- sysdeps_dir=i386
+ sysdeps_dir=x86-64
DIVIDESPEC=-f%{m32:no-}%{!m32:%{!m64:no-}}%{m64:}use-divide-subroutine
;;
mips-sgi-irix6* )
/* locks.h - Thread synchronization primitives. X86/x86-64 implementation.
- Copyright (C) 2002, 2011 Free Software Foundation
+ Copyright (C) 2002 Free Software Foundation
This file is part of libgcj.
obj_addr_t old,
obj_addr_t new_val)
{
- return __sync_bool_compare_and_swap (addr, old, new_val);
-}
-
-// Ensure that subsequent instructions do not execute on stale
-// data that was loaded from memory before the barrier.
-// On X86/x86-64, the hardware ensures that reads are properly ordered.
-inline static void
-read_barrier()
-{
-}
-
-// Ensure that prior stores to memory are completed with respect to other
-// processors.
-inline static void
-write_barrier()
-{
- /* x86-64/X86 does not reorder writes. We just need to ensure that
- gcc also doesn't. */
- __asm__ __volatile__(" " : : : "memory");
+ char result;
+#ifdef __x86_64__
+ __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
+ : "=m"(*(addr)), "=q"(result)
+ : "r" (new_val), "a"(old), "m"(*addr)
+ : "memory");
+#else
+ __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
+ : "=m"(*addr), "=q"(result)
+ : "r" (new_val), "a"(old), "m"(*addr)
+ : "memory");
+#endif
+ return (bool) result;
}
// Set *addr to new_val with release semantics, i.e. making sure
inline static void
release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
{
- write_barrier ();
+ __asm__ __volatile__(" " : : : "memory");
*(addr) = new_val;
}
{
return compare_and_swap(addr, old, new_val);
}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+// On X86/x86-64, the hardware ensures that reads are properly ordered.
+inline static void
+read_barrier()
+{
+}
+
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+inline static void
+write_barrier()
+{
+ /* x86-64/X86 does not reorder writes. We just need to ensure that
+ gcc also doesn't. */
+ __asm__ __volatile__(" " : : : "memory");
+}
#endif
--- /dev/null
+/* locks.h - Thread synchronization primitives. X86/x86-64 implementation.
+
+ Copyright (C) 2002 Free Software Foundation
+
+ Contributed by Bo Thorsen <bo@suse.de>.
+
+ This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
+details. */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+typedef size_t obj_addr_t; /* Integer type big enough for object */
+ /* address. */
+
+// Atomically replace *addr by new_val if it was initially equal to old.
+// Return true if the comparison succeeded.
+// Assumed to have acquire semantics, i.e. later memory operations
+// cannot execute before the compare_and_swap finishes.
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ char result;
+#ifdef __x86_64__
+ __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
+ : "=m"(*(addr)), "=q"(result)
+ : "r" (new_val), "a"(old), "m"(*addr)
+ : "memory");
+#else
+ __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
+ : "=m"(*addr), "=q"(result)
+ : "r" (new_val), "a"(old), "m"(*addr)
+ : "memory");
+#endif
+ return (bool) result;
+}
+
+// Set *addr to new_val with release semantics, i.e. making sure
+// that prior loads and stores complete before this
+// assignment.
+// On X86/x86-64, the hardware shouldn't reorder reads and writes,
+// so we just have to convince gcc not to do it either.
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+ __asm__ __volatile__(" " : : : "memory");
+ *(addr) = new_val;
+}
+
+// Compare_and_swap with release semantics instead of acquire semantics.
+// On many architecture, the operation makes both guarantees, so the
+// implementation can be the same.
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ return compare_and_swap(addr, old, new_val);
+}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+// On X86/x86-64, the hardware ensures that reads are properly ordered.
+inline static void
+read_barrier()
+{
+}
+
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+inline static void
+write_barrier()
+{
+ /* x86-64/X86 does not reorder writes. We just need to ensure that
+ gcc also doesn't. */
+ __asm__ __volatile__(" " : : : "memory");
+}
+#endif
projects / gcc.git / commitdiff