src/cpu/o3/alpha_dyn_inst_impl.hh:
Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
Only include checker if it's being used.
--HG--
extra : convert_revision :
aae0bf1e19baae90f1e61d41191548612bbb3be6
Fault
AlphaDynInst<Impl>::completeAcc(Packet *pkt)
{
- if (this->isLoad()) {
- this->fault = this->staticInst->completeAcc(pkt, this,
- this->traceData);
- } else if (this->isStore()) {
- this->fault = this->staticInst->completeAcc(pkt, this,
- this->traceData);
- } else {
- panic("Unknown type!");
- }
+ this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
return this->fault;
}
#include "base/loader/symtab.hh"
#include "base/timebuf.hh"
-#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/thread_state.hh"
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
using namespace std;
template <class Impl>
++fetchIcacheSquashes;
delete pkt->req;
delete pkt;
- memReq[tid] = NULL;
return;
}
/** Writes back stores. */
void writebackStores();
+ /** Completes the data access that has been returned from the
+ * memory system. */
void completeDataAccess(PacketPtr pkt);
/** Clears all the entries in the LQ. */
#include "config/use_checker.hh"
-#include "cpu/checker/cpu.hh"
#include "cpu/o3/lsq_unit.hh"
#include "base/str.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
template<class Impl>
LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
LSQUnit *lsq_ptr)