re PR target/70669 (PowerPC __float128 does not support direct move)
authorMichael Meissner <meissner@linux.vnet.ibm.com>
Thu, 14 Apr 2016 23:21:30 +0000 (23:21 +0000)
committerMichael Meissner <meissner@gcc.gnu.org>
Thu, 14 Apr 2016 23:21:30 +0000 (23:21 +0000)
[gcc]
2016-04-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/70669
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add
direct move handlers for KFmode. Change TFmode handlers test from
FLOAT128_IEEE_P to FLOAT128_VECTOR_P.

[gcc/testsuite]
2016-04-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/70669
* gcc.target/powerpc/pr70669.c: New test.

From-SVN: r234995

gcc/ChangeLog
gcc/config/rs6000/rs6000.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/pr70669.c [new file with mode: 0644]

index 8f5f3207232b425bbd8ed12c3583aefc68cc6c1b..f6fdeffcc53538ac63ae0921ba46b893de9acf01 100644 (file)
@@ -1,3 +1,10 @@
+2016-04-14  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/70669
+       * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add
+       direct move handlers for KFmode. Change TFmode handlers test from
+       FLOAT128_IEEE_P to FLOAT128_VECTOR_P.
+
 2016-04-14  Jakub Jelinek  <jakub@redhat.com>
 
        PR c++/70594
index c63fa06aa1a07a0728c59175024b4fbb4608c141..1d0076c41f0f1f08ef10f306efd1ec3aca4ea6a6 100644 (file)
@@ -3132,8 +3132,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
          reg_addr[V4SFmode].reload_load   = CODE_FOR_reload_v4sf_di_load;
          reg_addr[V2DFmode].reload_store  = CODE_FOR_reload_v2df_di_store;
          reg_addr[V2DFmode].reload_load   = CODE_FOR_reload_v2df_di_load;
-         reg_addr[KFmode].reload_store    = CODE_FOR_reload_kf_di_store;
-         reg_addr[KFmode].reload_load     = CODE_FOR_reload_kf_di_load;
          reg_addr[DFmode].reload_store    = CODE_FOR_reload_df_di_store;
          reg_addr[DFmode].reload_load     = CODE_FOR_reload_df_di_load;
          reg_addr[DDmode].reload_store    = CODE_FOR_reload_dd_di_store;
@@ -3141,7 +3139,13 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
          reg_addr[SFmode].reload_store    = CODE_FOR_reload_sf_di_store;
          reg_addr[SFmode].reload_load     = CODE_FOR_reload_sf_di_load;
 
-         if (FLOAT128_IEEE_P (TFmode))
+         if (FLOAT128_VECTOR_P (KFmode))
+           {
+             reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
+             reg_addr[KFmode].reload_load  = CODE_FOR_reload_kf_di_load;
+           }
+
+         if (FLOAT128_VECTOR_P (TFmode))
            {
              reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
              reg_addr[TFmode].reload_load  = CODE_FOR_reload_tf_di_load;
@@ -3182,6 +3186,18 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
              reg_addr[V8HImode].reload_vsx_gpr  = CODE_FOR_reload_vsx_from_gprv8hi;
              reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
              reg_addr[SFmode].reload_vsx_gpr    = CODE_FOR_reload_vsx_from_gprsf;
+
+             if (FLOAT128_VECTOR_P (KFmode))
+               {
+                 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
+                 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
+               }
+
+             if (FLOAT128_VECTOR_P (TFmode))
+               {
+                 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
+                 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
+               }
            }
        }
       else
@@ -3200,8 +3216,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
          reg_addr[V4SFmode].reload_load   = CODE_FOR_reload_v4sf_si_load;
          reg_addr[V2DFmode].reload_store  = CODE_FOR_reload_v2df_si_store;
          reg_addr[V2DFmode].reload_load   = CODE_FOR_reload_v2df_si_load;
-         reg_addr[KFmode].reload_store    = CODE_FOR_reload_kf_si_store;
-         reg_addr[KFmode].reload_load     = CODE_FOR_reload_kf_si_load;
          reg_addr[DFmode].reload_store    = CODE_FOR_reload_df_si_store;
          reg_addr[DFmode].reload_load     = CODE_FOR_reload_df_si_load;
          reg_addr[DDmode].reload_store    = CODE_FOR_reload_dd_si_store;
@@ -3209,6 +3223,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
          reg_addr[SFmode].reload_store    = CODE_FOR_reload_sf_si_store;
          reg_addr[SFmode].reload_load     = CODE_FOR_reload_sf_si_load;
 
+         if (FLOAT128_VECTOR_P (KFmode))
+           {
+             reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
+             reg_addr[KFmode].reload_load  = CODE_FOR_reload_kf_si_load;
+           }
+
          if (FLOAT128_IEEE_P (TFmode))
            {
              reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
index 4b68cb309b6c36232a10f655cdd9209dddbc07ed..4131b9fcfe466d84c6212a6c5193e7df00f7931d 100644 (file)
@@ -1,5 +1,8 @@
 2016-04-14  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
+       PR target/70669
+       * gcc.target/powerpc/pr70669.c: New test.
+
        PR target/70640
        * gcc.target/powerpc/pr70640.c: Fix test so it correctly works on
        a power7 system that does not have an assembler that supports
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70669.c b/gcc/testsuite/gcc.target/powerpc/pr70669.c
new file mode 100644 (file)
index 0000000..8054102
--- /dev/null
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-O2 -mcpu=power8 -mfloat128" } */
+
+#ifndef TYPE
+#define TYPE __float128
+#endif
+
+void foo (TYPE *p, TYPE *q)
+{
+  TYPE r = *q;
+#ifndef NO_ASM
+  __asm__ (" # %0" : "+r" (r));
+#endif
+  *p = r;
+}
+
+/* { dg-final { scan-assembler       "mfvsrd"    } } */
+/* { dg-final { scan-assembler       "mtvsrd"    } } */
+/* { dg-final { scan-assembler-times "stxvd2x" 1 } } */
+/* { dg-final { scan-assembler-times "lxvd2x"  1 } } */