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AVX-512. Add mov[dlh]dup insns support.
authorAlexander Ivchenko <alexander.ivchenko@intel.com>
Thu, 25 Sep 2014 08:21:17 +0000 (08:21 +0000)
committerKirill Yukhin <kyukhin@gcc.gnu.org>
Thu, 25 Sep 2014 08:21:17 +0000 (08:21 +0000)
gcc/
* config/i386/sse.md
(define_insn "avx_movshdup256<mask_name>"): Add masking.
(define_insn "sse3_movshdup<mask_name>"): Ditto.
(define_insn "avx_movsldup256<mask_name>"): Ditto.
(define_insn "sse3_movsldup<mask_name>"): Ditto.
(define_insn "vec_dupv2df<mask_name>"): Ditto.
(define_insn "*vec_concatv2df"): Add EVEX version.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r215589

gcc/ChangeLog patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a1ad37989cbd451cd83ffa729e28cab55675c01c..8e357ac07338265018d467eb89ab7cc4aea5eaf9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2014-09-25  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/sse.md
+       (define_insn "avx_movshdup256<mask_name>"): Add masking.
+       (define_insn "sse3_movshdup<mask_name>"): Ditto.
+       (define_insn "avx_movsldup256<mask_name>"): Ditto.
+       (define_insn "sse3_movsldup<mask_name>"): Ditto.
+       (define_insn "vec_dupv2df<mask_name>"): Ditto.
+       (define_insn "*vec_concatv2df"): Add EVEX version.
+
 2014-09-25  Alexander Ivchenko  <alexander.ivchenko@intel.com>
            Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
            Anna Tikhonova  <anna.tikhonova@intel.com>
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 09fb2631b853feb78547a3be3a6edc0fe755a0ec..0ed93335871f4d4bca9b6c588de8ad0d6cb1fd83 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5735,34 +5735,34 @@
 
 ;; These are modeled with the same vec_concat as the others so that we
 ;; capture users of shufps that can use the new instructions
-(define_insn "avx_movshdup256"
-  [(set (match_operand:V8SF 0 "register_operand" "=x")
+(define_insn "avx_movshdup256<mask_name>"
+  [(set (match_operand:V8SF 0 "register_operand" "=v")
        (vec_select:V8SF
          (vec_concat:V16SF
-           (match_operand:V8SF 1 "nonimmediate_operand" "xm")
+           (match_operand:V8SF 1 "nonimmediate_operand" "vm")
            (match_dup 1))
          (parallel [(const_int 1) (const_int 1)
                     (const_int 3) (const_int 3)
                     (const_int 5) (const_int 5)
                     (const_int 7) (const_int 7)])))]
-  "TARGET_AVX"
-  "vmovshdup\t{%1, %0|%0, %1}"
+  "TARGET_AVX && <mask_avx512vl_condition>"
+  "vmovshdup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "sse")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
-(define_insn "sse3_movshdup"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
+(define_insn "sse3_movshdup<mask_name>"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
        (vec_select:V4SF
          (vec_concat:V8SF
-           (match_operand:V4SF 1 "nonimmediate_operand" "xm")
+           (match_operand:V4SF 1 "nonimmediate_operand" "vm")
            (match_dup 1))
          (parallel [(const_int 1)
                     (const_int 1)
                     (const_int 7)
                     (const_int 7)])))]
-  "TARGET_SSE3"
-  "%vmovshdup\t{%1, %0|%0, %1}"
+  "TARGET_SSE3 && <mask_avx512vl_condition>"
+  "%vmovshdup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "sse")
    (set_attr "prefix_rep" "1")
    (set_attr "prefix" "maybe_vex")
@@ -5788,34 +5788,34 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "V16SF")])
 
-(define_insn "avx_movsldup256"
-  [(set (match_operand:V8SF 0 "register_operand" "=x")
+(define_insn "avx_movsldup256<mask_name>"
+  [(set (match_operand:V8SF 0 "register_operand" "=v")
        (vec_select:V8SF
          (vec_concat:V16SF
-           (match_operand:V8SF 1 "nonimmediate_operand" "xm")
+           (match_operand:V8SF 1 "nonimmediate_operand" "vm")
            (match_dup 1))
          (parallel [(const_int 0) (const_int 0)
                     (const_int 2) (const_int 2)
                     (const_int 4) (const_int 4)
                     (const_int 6) (const_int 6)])))]
-  "TARGET_AVX"
-  "vmovsldup\t{%1, %0|%0, %1}"
+  "TARGET_AVX && <mask_avx512vl_condition>"
+  "vmovsldup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "sse")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
-(define_insn "sse3_movsldup"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
+(define_insn "sse3_movsldup<mask_name>"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
        (vec_select:V4SF
          (vec_concat:V8SF
-           (match_operand:V4SF 1 "nonimmediate_operand" "xm")
+           (match_operand:V4SF 1 "nonimmediate_operand" "vm")
            (match_dup 1))
          (parallel [(const_int 0)
                     (const_int 0)
                     (const_int 6)
                     (const_int 6)])))]
-  "TARGET_SSE3"
-  "%vmovsldup\t{%1, %0|%0, %1}"
+  "TARGET_SSE3 && <mask_avx512vl_condition>"
+  "%vmovsldup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "sse")
    (set_attr "prefix_rep" "1")
    (set_attr "prefix" "maybe_vex")
@@ -8301,24 +8301,24 @@
    (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")
    (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
 
-(define_insn "vec_dupv2df"
-  [(set (match_operand:V2DF 0 "register_operand"     "=x,x")
+(define_insn "vec_dupv2df<mask_name>"
+  [(set (match_operand:V2DF 0 "register_operand"     "=x,v")
        (vec_duplicate:V2DF
-         (match_operand:DF 1 "nonimmediate_operand" " 0,xm")))]
-  "TARGET_SSE2"
+         (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))]
+  "TARGET_SSE2 && <mask_avx512vl_condition>"
   "@
    unpcklpd\t%0, %0
-   %vmovddup\t{%1, %0|%0, %1}"
+   %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,sse3")
    (set_attr "type" "sselog1")
    (set_attr "prefix" "orig,maybe_vex")
    (set_attr "mode" "V2DF,DF")])
 
 (define_insn "*vec_concatv2df"
-  [(set (match_operand:V2DF 0 "register_operand"     "=x,x,x,x,x,x,x,x")
+  [(set (match_operand:V2DF 0 "register_operand"     "=x,v,v,x,x,v,x,x")
        (vec_concat:V2DF
-         (match_operand:DF 1 "nonimmediate_operand" " 0,x,m,0,x,m,0,0")
-         (match_operand:DF 2 "vector_move_operand"  " x,x,1,m,m,C,x,m")))]
+         (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0")
+         (match_operand:DF 2 "vector_move_operand"  " x,v,1,m,m,C,x,m")))]
   "TARGET_SSE"
   "@
    unpcklpd\t{%2, %0|%0, %2}