(no commit message)

diff --git a/nlnet_2021_lip6_vlsi.mdwn b/nlnet_2021_lip6_vlsi.mdwn
index 1a3f7ba3677a60596b9bfc0279f6954c598be4c2..4f2cde93f00e74e1e0719b37c16a6a406160586b 100644 (file)
--- a/nlnet_2021_lip6_vlsi.mdwn
+++ b/nlnet_2021_lip6_vlsi.mdwn
@@ -26,11 +26,16 @@ engendered and fostered where at present NDAs rife through the VLSI
 Industry prevent and prohibit discussion and general improvements beneficial
 to users.
 
-
+The expected outcome is to improve Coriolis2, HITAS/TAGLE and extend the
+whole toolchain so that it is faster, able to handle larger ASIC designs,
+and can perform Logical Validation. Also to be improved and tested is
+support for lower geometries (starting with 130nm)
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
-
+LIP6 has created the ASIC Layout for the Libre-SOC 180nm ASIC that went to
+IMEC TSMC MPW in June 2021.  It was developed entirely with Libre source code
+from HDL to GDS-II, the only NDA being the TSMC PDK.
 
 
 # Requested Amount    
@@ -42,10 +47,16 @@ EUR $50,000.
 
 # Does the project have other funding sources, both past and present?
 
-
+LIP6 is part of Sorbonne University.  The developers and maintainers
+of Coriolis2, HITAS/TAGLE, and Alliance, are all employed by Sorbonne
+University.
 
 # Compare your own project with existing or historical efforts.
 
+The only other major proven VLSI Toolchain that is Libre Licensed and
+has created successful ASICs is Magic, selected as part of the OpenROAD
+toolchain.  The entire OpenROAD toolchain is based on tcl/tk, a 1980s
+scripting language technology
 
 ## What are significant technical challenges you expect to solve during the project, if any?