);
always @* begin
case (x)
- 0, 2: o = b;
+ //0, 2: o = b;
+ 0: o = b;
+ 2: o = b;
1: o = c;
default: begin
o = a;
endcase
end
endmodule
+
+module case_nonoverlap (
+ input wire [2:0] x,
+ input wire a, b, c, d, e, f, g,
+ output reg o
+);
+ always @* begin
+ case (x)
+ //0, 2: o = b; // Creates $reduce_or
+ //0: o = b; 2: o = b; // Creates $reduce_or
+ 0: o = b;
+ 2: o = f;
+ 1: o = c;
+ default:
+ case (x)
+ //3, 4: o = d; // Creates $reduce_or
+ //3: o = d; 4: o = d; // Creates $reduce_or
+ 3: o = d;
+ 4: o = g;
+ 5: o = e;
+ default: o = 1'b0;
+ endcase
+ endcase
+ end
+endmodule
+
+module case_overlap (
+ input wire [2:0] x,
+ input wire a, b, c, d, e, f, g,
+ output reg o
+);
+ always @* begin
+ case (x)
+ //0, 2: o = b; // Creates $reduce_or
+ //0: o = b; 2: o = b; // Creates $reduce_or
+ 0: o = b;
+ 2: o = f;
+ 1: o = c;
+ default:
+ case (x)
+ //3, 4: o = d; // Creates $reduce_or
+ //3: o = d; 4: o = d; // Creates $reduce_or
+ 2: o = 1'b1; // Overlaps with previous $pmux
+ 3: o = d;
+ 4: o = g;
+ 5: o = e;
+ default: o = 1'b0;
+ endcase
+ endcase
+ end
+endmodule
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_nonoverlap
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_overlap
+prep
+design -save gold
+muxpack
+#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter