soc: increase supporteds address_width/paging

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 82589a72c6322f69998cada1a7eb9cb9d2bdbc41..91c3306dd5c4790a4faff883eae1cbd2062fee3a 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -426,9 +426,9 @@ class SoCLocHandler(Module):
 
 class SoCCSRHandler(SoCLocHandler):
     supported_data_width    = [8, 32]
-    supported_address_width = [14, 15]
+    supported_address_width = [14+i for i in range(4)]
     supported_alignment     = [32, 64]
-    supported_paging        = [0x800*2**i for i in range(3)]
+    supported_paging        = [0x800*2**i for i in range(4)]
 
     # Creation -------------------------------------------------------------------------------------
     def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):