-- We don't do pipelining yet.
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
- -- Use alternate core reset address set when DRAM is not initialized.
+ -- Reset ignored, the reset controller use the pll lock signal,
+ -- and alternate core reset address set when DRAM is not initialized.
+ --
core_alt_reset <= not init_done;
-- State machine
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:26
+// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 13:30:46
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
-- We don't do pipelining yet.
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
- -- Use alternate core reset address set when DRAM is not initialized.
+ -- Reset ignored, the reset controller use the pll lock signal,
+ -- and alternate core reset address set when DRAM is not initialized.
+ --
core_alt_reset <= not init_done;
-- State machine
38c101987c651b78
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3821017060000000
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0100000000000000
4e80002000000280
0000000000000000
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:28
+// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 13:30:49
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,