Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
#else
- Ra = curTick;
+ Ra = curTick();
#endif
}}, IsUnverifiable);
Linux::ThreadInfo(tc).curTaskPID());
_modeGood[newmode]++;
- _modeTicks[themode] += curTick - lastModeTick;
+ _modeTicks[themode] += curTick() - lastModeTick;
- lastModeTick = curTick;
+ lastModeTick = curTick();
themode = newmode;
}
TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr);
const int clk_hz = one_million;
- elp->si_user = htog(curTick / (SimClock::Frequency / clk_hz));
+ elp->si_user = htog(curTick() / (SimClock::Frequency / clk_hz));
elp->si_nice = htog(0);
elp->si_sys = htog(0);
elp->si_idle = htog(0);
TableWalker::nextWalk(ThreadContext *tc)
{
if (pendingQueue.size())
- schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick+1));
+ schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1));
}
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
- cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
+ cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
}
}
void
ISA::CP0Event::scheduleEvent(int delay)
{
- cpu->reschedule(this, curTick + cpu->ticks(delay), true);
+ cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
}
void
def format MT_MFTR(code, *flags) {{
flags += ('IsNonSpeculative', )
-# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
code += 'if (MT_H == 1) {\n'
code += 'data = bits(data, top_bit, bottom_bit);\n'
def format MT_MTTR(code, *flags) {{
flags += ('IsNonSpeculative', )
-# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
iop = InstObjParams(name, Name, 'MTOp', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
if (stCondFailures % 100000 == 0) {
warn("%i: context %d: %d consecutive "
"store conditional failures\n",
- curTick, xc->contextId(), stCondFailures);
+ curTick(), xc->contextId(), stCondFailures);
}
if (!lock_flag){
tc->setMiscReg(MISCREG_TC_RESTART, pc.npc());
warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
- curTick, tc->threadId(), tc->getCpuPtr()->name(),
+ curTick(), tc->threadId(), tc->getCpuPtr()->name(),
pc.pc(), pc.npc());
}
}
tc->activate(0);
warn("%i: Restoring thread %i in %s @ PC %x",
- curTick, tc->threadId(), tc->getCpuPtr()->name(), restartPC);
+ curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
}
}
tcStatus.a = 0;
tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
warn("%i: Deactivating Hardware Thread Context #%i",
- curTick, tc->threadId());
+ curTick(), tc->threadId());
}
} else if (src_reg > 0) {
if (src_reg && !yield_mask != 0) {
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
cpu->deschedule(tickCompare);
- cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
+ cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
}
panic("writing to TICK compare register %#X\n", val);
break;
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
cpu->deschedule(sTickCompare);
- cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
+ cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
cpu->deschedule(hSTickCompare);
- cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
+ cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else {
- cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
+ cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
}
}
}
// Need to do something to cause interrupt to happen here !!! @todo
} else {
- cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
+ cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
}
}
uint64_t ticksPerCount = clock *
divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
// Compute how many m5 ticks are left.
- uint64_t val = apicTimerEvent.when() - curTick;
+ uint64_t val = apicTimerEvent.when() - curTick();
// Turn that into a count.
val = (val + ticksPerCount - 1) / ticksPerCount;
return val;
uint64_t newCount = newVal *
(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
// Schedule on the edge of the next tick plus the new count.
- Tick offset = curTick % clock;
+ Tick offset = curTick() % clock;
if (offset) {
reschedule(apicTimerEvent,
- curTick + (newCount + 1) * clock - offset, true);
+ curTick() + (newCount + 1) * clock - offset, true);
} else {
reschedule(apicTimerEvent,
- curTick + newCount * clock, true);
+ curTick() + newCount * clock, true);
}
}
break;
StringWrap name(sys->name());
if (!sm[0])
- warn("Got null SM at tick %d\n", curTick);
+ warn("Got null SM at tick %d\n", curTick());
int sysi = getSys(sys);
int smi = getSm(sysi, sm, args[1]);
DPRINTF(Annotate, "Ending machine: %s; end stack: %s\n", sm,
smMap[smib-1].second.first);
- warn("State machine stack not unwinding correctly at %d\n", curTick);
+ warn("State machine stack not unwinding correctly at %d\n", curTick());
} else {
DPRINTF(Annotate,
"State machine ending:%s sysi:%d id:%#x back:%d getSm:%d\n",
DPRINTF(Annotate, "Explict begin of state %s\n", st);
uint32_t flags = args[0];
if (flags & FL_BAD)
- warn("BAD state encountered: at cycle %d: %s\n", curTick, st);
+ warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
swBegin(tc->getSystemPtr(), tc->contextId(), st, getFrame(tc), true, args[0]);
}
warn("%d: Queue Assert: SW said there should be %d byte(s) in %s,"
"however there are %d byte(s)\n",
- curTick, size, q, qBytes[qi-1]);
+ curTick(), size, q, qBytes[qi-1]);
DPRINTF(AnnotateQ, "%d: Queue Assert: SW said there should be %d"
" byte(s) in %s, however there are %d byte(s)\n",
- curTick, size, q, qBytes[qi-1]);
+ curTick(), size, q, qBytes[qi-1]);
}
}
CPA::add(int t, int f, int c, int sm, int stq, int32_t d)
{
AnnDataPtr an = new AnnotateData;
- an->time = curTick;
+ an->time = curTick();
an->data = d;
an->orig_data = d;
an->op = t;
int smi = getSm(sysi, sm, frame);
add(OP_BEGIN, FL_HW | f, 0, smi, getSt(sm, st));
if (f & FL_BAD)
- warn("BAD state encountered: at cycle %d: %s\n", curTick, st);
+ warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
}
inline void hwQ(flags f, System *sys, uint64_t frame, std::string sm,
#include <typeinfo>
#include "base/cprintf.hh"
-#include "sim/core.hh" // for curTick
+#include "sim/core.hh" // for curTick()
using namespace std;
{
// mark this object in use
inUse = true;
- whenAllocated = curTick;
+ whenAllocated = curTick();
// update count
++numInUse;
format += "Memory Usage: %ld KBytes\n";
format += "For more information see: http://www.m5sim.org/%s/%x\n";
- args.push_back(curTick);
+ args.push_back(curTick());
args.push_back(func);
args.push_back(file);
args.push_back(line);
if (verbose) {
format += " @ cycle %d\n[%s:%s, line %d]\n";
- args.push_back(curTick);
+ args.push_back(curTick());
args.push_back(func);
args.push_back(file);
args.push_back(line);
#ifndef NDEBUG
ccprintf(cerr, "%d: %s: listening for remote gdb #%d on port %d\n",
- curTick, name(), gdb->number, port);
+ curTick(), name(), gdb->number, port);
#else
ccprintf(cerr, "%d: %s: listening for remote gdb on port %d\n",
- curTick, name(), port);
+ curTick(), name(), port);
#endif
}
class Callback;
/** The current simulated tick. */
-extern Tick curTick;
+extern Tick curTick();
/* A namespace for all of the Statistics */
namespace Stats {
void
set(Counter val)
{
- total += current * (curTick - last);
- last = curTick;
+ total += current * (curTick() - last);
+ last = curTick();
current = val;
}
Result
result() const
{
- assert(last == curTick);
- return (Result)(total + current) / (Result)(curTick - lastReset + 1);
+ assert(last == curTick());
+ return (Result)(total + current) / (Result)(curTick() - lastReset + 1);
}
/**
void
prepare(Info *info)
{
- total += current * (curTick - last);
- last = curTick;
+ total += current * (curTick() - last);
+ last = curTick();
}
/**
reset(Info *info)
{
total = 0.0;
- last = curTick;
- lastReset = curTick;
+ last = curTick();
+ lastReset = curTick();
}
};
data.type = params->type;
data.sum = sum;
data.squares = squares;
- data.samples = curTick;
+ data.samples = curTick();
}
/**
configure();
// store sample #
- newdata.tick = curTick;
+ newdata.tick = curTick();
MySQL::Connection &mysql = run->conn();
void
dump()
{
- assert(lastDump <= curTick);
- if (lastDump == curTick)
+ assert(lastDump <= curTick());
+ if (lastDump == curTick())
return;
- lastDump = curTick;
+ lastDump = curTick();
prepare();
#define DDUMP(x, data, count) do { \
if (DTRACE(x)) \
- Trace::dump(curTick, name(), data, count); \
+ Trace::dump(curTick(), name(), data, count); \
} while (0)
#define DPRINTF(x, ...) do { \
if (DTRACE(x)) \
- Trace::dprintf(curTick, name(), __VA_ARGS__); \
+ Trace::dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
#define DPRINTFS(x,s, ...) do { \
if (DTRACE(x)) \
- Trace::dprintf(curTick, s->name(), __VA_ARGS__); \
+ Trace::dprintf(curTick(), s->name(), __VA_ARGS__); \
} while (0)
} while (0)
#define DDUMPN(data, count) do { \
- Trace::dump(curTick, name(), data, count); \
+ Trace::dump(curTick(), name(), data, count); \
} while (0)
#define DPRINTFN(...) do { \
- Trace::dprintf(curTick, name(), __VA_ARGS__); \
+ Trace::dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
#define DPRINTFNR(...) do { \
cpu(_cpu), _repeatEvent(true)
{
if (_interval)
- cpu->schedule(this, curTick + _interval);
+ cpu->schedule(this, curTick() + _interval);
}
void
ipc = 0.0;
#else
cprintf("%lli: %s progress event, total committed:%i, progress insts "
- "committed: %lli\n", curTick, cpu->name(), temp,
+ "committed: %lli\n", curTick(), cpu->name(), temp,
temp - lastNumInst);
#endif
lastNumInst = temp;
if (_repeatEvent)
- cpu->schedule(this, curTick + _interval);
+ cpu->schedule(this, curTick() + _interval);
}
const char *
phase(p->phase)
#endif
{
-// currentTick = curTick;
+// currentTick = curTick();
// if Python did not provide a valid ID, do it here
if (_cpuId == -1 ) {
{
#if FULL_SYSTEM
if (!params()->defer_registration && profileEvent)
- schedule(profileEvent, curTick);
+ schedule(profileEvent, curTick());
#endif
if (params()->progress_interval) {
Tick
BaseCPU::nextCycle()
{
- Tick next_tick = curTick - phase + clock - 1;
+ Tick next_tick = curTick() - phase + clock - 1;
next_tick -= (next_tick % clock);
next_tick += phase;
return next_tick;
next_tick = next_tick - (next_tick % clock) + clock;
next_tick += phase;
- assert(next_tick >= curTick);
+ assert(next_tick >= curTick());
return next_tick;
}
threadContexts[i]->profileClear();
if (profileEvent)
- schedule(profileEvent, curTick);
+ schedule(profileEvent, curTick());
#endif
// Connect new CPU to old CPU's memory only if new CPU isn't
tc->profileSample();
}
- cpu->schedule(this, curTick + interval);
+ cpu->schedule(this, curTick() + interval);
}
void
}
ccprintf(*functionTraceStream, " (%d)\n%d: %s",
- curTick - functionEntryTick, curTick, sym_str);
- functionEntryTick = curTick;
+ curTick() - functionEntryTick, curTick(), sym_str);
+ functionEntryTick = curTick();
}
}
// Tick currentTick;
inline Tick frequency() const { return SimClock::Frequency / clock; }
inline Tick ticks(int numCycles) const { return clock * numCycles; }
- inline Tick curCycle() const { return curTick / clock; }
+ inline Tick curCycle() const { return curTick() / clock; }
inline Tick tickToCycles(Tick val) const { return val / clock; }
// @todo remove me after debugging with legion done
Tick instCount() { return instCnt; }
/** The next cycle the CPU should be scheduled, given a cache
* access or quiesce event returning on this cycle. This function
- * may return curTick if the CPU should run on the current cycle.
+ * may return curTick() if the CPU should run on the current cycle.
*/
Tick nextCycle();
/** The next cycle the CPU should be scheduled, given a cache
* access or quiesce event returning on the given Tick. This
- * function may return curTick if the CPU should run on the
+ * function may return curTick() if the CPU should run on the
* current cycle.
* @param begin_tick The tick that the event is completing on.
*/
if (data != inst_data) {
warn("%lli: Store value does not match value in memory! "
"Instruction: %#x, memory: %#x",
- curTick, inst_data, data);
+ curTick(), inst_data, data);
handleError();
}
}
CheckerCPU::dumpAndExit()
{
warn("%lli: Checker PC:%#x, next PC:%#x",
- curTick, thread->readPC(), thread->readNextPC());
+ curTick(), thread->readPC(), thread->readNextPC());
panic("Checker found an error!");
}
} else {
warn("%lli: Changed PC does not match expected PC, "
"changed: %#x, expected: %#x",
- curTick, thread->readPC(), newPC);
+ curTick(), thread->readPC(), newPC);
CheckerCPU::handleError();
}
willChangePC = false;
// translate this instruction; in the SMT case it's
// possible that its ITB entry was kicked out.
warn("%lli: Instruction PC %#x was not found in the ITB!",
- curTick, thread->readPC());
+ curTick(), thread->readPC());
handleError(inst);
// go to the next instruction
{
if (inst->readPC() != thread->readPC()) {
warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
- curTick, inst->readPC(), thread->readPC());
+ curTick(), inst->readPC(), thread->readPC());
if (changedPC) {
warn("%lli: Changed PCs recently, may not be an error",
- curTick);
+ curTick());
} else {
handleError(inst);
}
if (mi != machInst) {
warn("%lli: Binary instructions do not match! Inst: %#x, "
"checker: %#x",
- curTick, mi, machInst);
+ curTick(), mi, machInst);
handleError(inst);
}
}
if (result_mismatch) {
warn("%lli: Instruction results do not match! (Values may not "
"actually be integers) Inst: %#x, checker: %#x",
- curTick, inst->readIntResult(), result.integer);
+ curTick(), inst->readIntResult(), result.integer);
// It's useful to verify load values from memory, but in MP
// systems the value obtained at execute may be different than
if (inst->readNextPC() != thread->readNextPC()) {
warn("%lli: Instruction next PCs do not match! Inst: %#x, "
"checker: %#x",
- curTick, inst->readNextPC(), thread->readNextPC());
+ curTick(), inst->readNextPC(), thread->readNextPC());
handleError(inst);
}
thread->readMiscRegNoEffect(misc_reg_idx)) {
warn("%lli: Misc reg idx %i (side effect) does not match! "
"Inst: %#x, checker: %#x",
- curTick, misc_reg_idx,
+ curTick(), misc_reg_idx,
inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
thread->readMiscRegNoEffect(misc_reg_idx));
handleError(inst);
{
if (updateThisCycle) {
warn("%lli: Instruction PC %#x results didn't match up, copying all "
- "registers from main CPU", curTick, unverifiedInst->readPC());
+ "registers from main CPU", curTick(), unverifiedInst->readPC());
// Heavy-weight copying of all registers
thread->copyArchRegs(unverifiedInst->tcBase());
// Also advance the PC. Hopefully no PC-based events happened.
InOrderCPU::CPUEvent::scheduleEvent(int delay)
{
assert(!scheduled() || squashed());
- cpu->reschedule(this, cpu->nextCycle(curTick + cpu->ticks(delay)), true);
+ cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
}
void
dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyBufferInst->setSquashed();
- lastRunningCycle = curTick;
+ lastRunningCycle = curTick();
// Reset CPU to reset state.
#if FULL_SYSTEM
if (!tickEvent.scheduled()) {
if (_status == SwitchedOut) {
// increment stat
- lastRunningCycle = curTick;
+ lastRunningCycle = curTick();
} else if (!activityRec.active()) {
DPRINTF(InOrderCPU, "sleeping CPU.\n");
- lastRunningCycle = curTick;
+ lastRunningCycle = curTick();
timesIdled++;
} else {
- //Tick next_tick = curTick + cycles(1);
+ //Tick next_tick = curTick() + cycles(1);
//tickEvent.schedule(next_tick);
- schedule(&tickEvent, nextCycle(curTick + 1));
+ schedule(&tickEvent, nextCycle(curTick() + 1));
DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
- nextCycle(curTick + 1));
+ nextCycle(curTick() + 1));
}
}
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
event_pri_offset);
- Tick sked_tick = nextCycle(curTick + ticks(delay));
+ Tick sked_tick = nextCycle(curTick() + ticks(delay));
if (delay >= 0) {
DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
- eventNames[c_event], curTick + delay, tid);
+ eventNames[c_event], curTick() + delay, tid);
schedule(cpu_event, sked_tick);
} else {
cpu_event->process();
activateThreadInPipeline(tid);
- thread[tid]->lastActivate = curTick;
+ thread[tid]->lastActivate = curTick();
tcBase(tid)->setStatus(ThreadContext::Active);
tid);
deactivateThread(tid);
suspendedThreads.push_back(tid);
- thread[tid]->lastSuspend = curTick;
+ thread[tid]->lastSuspend = curTick();
tcBase(tid)->setStatus(ThreadContext::Suspended);
}
// Finalize Trace Data For Instruction
if (inst->traceData) {
- //inst->traceData->setCycle(curTick);
+ //inst->traceData->setCycle(curTick());
inst->traceData->setFetchSeq(inst->seqNum);
//inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
inst->traceData->dump();
DPRINTF(Activity, "Waking up CPU\n");
- Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
+ Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
idleCycles += extra_cycles;
for (int stage_num = 0; stage_num < NumStages; stage_num++) {
numCycles += extra_cycles;
- schedule(&tickEvent, nextCycle(curTick));
+ schedule(&tickEvent, nextCycle(curTick()));
}
#if FULL_SYSTEM
void scheduleTickEvent(int delay)
{
assert(!tickEvent.scheduled() || tickEvent.squashed());
- reschedule(&tickEvent, nextCycle(curTick + ticks(delay)), true);
+ reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
}
/** Unschedule tick event, regardless of its current state. */
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
- instResult[idx].tick = curTick;
+ instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
"being set to %#x.\n", threadNumber, seqNum, idx, val);
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
- instResult[idx].tick = curTick;
+ instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
"being set to %#x (result-tick:%i).\n",
{
instResult[idx].val.dbl = val;
instResult[idx].type = Float;
- instResult[idx].tick = curTick;
+ instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
- instResult[idx].tick = curTick;
+ instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",
PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
{
if (cpu->squashSeqNum[tid] < inst->seqNum &&
- cpu->lastSquashCycle[tid] == curTick){
+ cpu->lastSquashCycle[tid] == curTick()){
DPRINTF(Resource, "Ignoring [sn:%i] branch squash signal due to "
"another stage's squash signal for after [sn:%i].\n",
inst->seqNum, cpu->squashSeqNum[tid]);
// Save squash num for later stage use
cpu->squashSeqNum[tid] = squash_seq_num;
- cpu->lastSquashCycle[tid] = curTick;
+ cpu->lastSquashCycle[tid] = curTick();
}
}
inst->popSchedEntry();
} else {
panic("%i: encountered %s fault!\n",
- curTick, req->fault->name());
+ curTick(), req->fault->name());
}
reqs_processed++;
if (nextStageQueueValid(inst->nextStage - 1)) {
if (inst->seqNum > cpu->squashSeqNum[tid] &&
- curTick == cpu->lastSquashCycle[tid]) {
+ curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, skipping "
"insertion into stage %i queue.\n", tid, inst->seqNum,
inst->nextStage);
// Take note of trace data for this inst & stage
if (inst->traceData) {
- inst->traceData->setStageCycle(stageNum, curTick);
+ inst->traceData->setStageCycle(stageNum, curTick());
}
}
assert(dest_reg_idx != -1);
if (forward_inst->isExecuted() &&
- forward_inst->readResultTime(dest_reg_idx) < curTick) {
+ forward_inst->readResultTime(dest_reg_idx) < curTick()) {
return forward_inst;
} else {
if (!forward_inst->isExecuted()) {
DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
"forwarding, [sn:%i] has not been executed yet.\n",
inst->seqNum, forward_inst->seqNum);
- } else if (forward_inst->readResultTime(dest_reg_idx) >= curTick) {
+ } else if (forward_inst->readResultTime(dest_reg_idx) >= curTick()) {
DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
"forwarding, [sn:%i] executed on tick:%i.\n",
inst->seqNum, forward_inst->seqNum,
DPRINTF(Resource, "[tid:%i]: Scheduling event for [sn:%i] on tick %i.\n",
reqMap[slot_idx]->inst->readTid(),
reqMap[slot_idx]->inst->seqNum,
- cpu->ticks(delay) + curTick);
+ cpu->ticks(delay) + curTick());
resourceEvent[slot_idx].scheduleEvent(delay);
}
{
assert(!scheduled() || squashed());
resource->cpu->reschedule(this,
- curTick + resource->ticks(delay), true);
+ curTick() + resource->ticks(delay), true);
}
case InOrderCPU::ActivateThread:
{
DPRINTF(Resource, "Scheduling Activate Thread Resource Pool Event for tick %i.\n",
- curTick + delay);
+ curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->bdelaySeqNum,
inst->readTid());
- res_pool_event->schedule(curTick + cpu->cycles(delay));
+ res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
case InOrderCPU::DeallocateThread:
{
DPRINTF(Resource, "Scheduling Deactivate Thread Resource Pool Event for tick %i.\n",
- curTick + delay);
+ curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->bdelaySeqNum,
tid);
- res_pool_event->schedule(curTick + cpu->cycles(delay));
+ res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
case ResourcePool::InstGraduated:
{
DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool Event for tick %i.\n",
- curTick + delay);
+ curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->seqNum,
inst->readTid());
- res_pool_event->schedule(curTick + cpu->cycles(delay));
+ res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
case ResourcePool::SquashAll:
{
DPRINTF(Resource, "Scheduling Squash Resource Pool Event for tick %i.\n",
- curTick + delay);
+ curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->bdelaySeqNum,
inst->readTid());
- res_pool_event->schedule(curTick + cpu->cycles(delay));
+ res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
ResourcePool::ResPoolEvent::scheduleEvent(int delay)
{
if (squashed())
- reschedule(curTick + resPool->cpu->cycles(delay));
+ reschedule(curTick() + resPool->cpu->cycles(delay));
else if (!scheduled())
- schedule(curTick + resPool->cpu->cycles(delay));
+ schedule(curTick() + resPool->cpu->cycles(delay));
}
/** Unschedule resource event, regardless of its current state. */
{
assert(delay >= 0);
- Tick when = cpu->nextCycle(curTick + cpu->ticks(delay));
+ Tick when = cpu->nextCycle(curTick() + cpu->ticks(delay));
switch (e_type)
{
case InOrderCPU::ActivateThread:
{
DPRINTF(Resource, "Scheduling Activate Thread Resource Pool Event "
- "for tick %i, [tid:%i].\n", curTick + delay,
+ "for tick %i, [tid:%i].\n", curTick() + delay,
inst->readTid());
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,
{
DPRINTF(Resource, "Scheduling Deactivate Thread Resource Pool "
- "Event for tick %i.\n", curTick + delay);
+ "Event for tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,
e_type,
case ResourcePool::InstGraduated:
{
DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool "
- "Event for tick %i.\n", curTick + delay);
+ "Event for tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
case ResourcePool::SquashAll:
{
DPRINTF(Resource, "Scheduling Squash Resource Pool Event for "
- "tick %i.\n", curTick + delay);
+ "tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
{
DPRINTF(Resource, "Scheduling Squash Due to Memory Stall Resource "
"Pool Event for tick %i.\n",
- curTick + delay);
+ curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
{
DPRINTF(Resource, "Scheduling UpdatePC Resource Pool Event "
"for tick %i.\n",
- curTick + delay);
+ curTick() + delay);
ResPoolEvent *res_pool_event = new ResPoolEvent(this,e_type,
inst,
inst->squashingStage,
{
InOrderCPU *cpu = resPool->cpu;
assert(!scheduled() || squashed());
- cpu->reschedule(this, cpu->nextCycle(curTick + cpu->ticks(delay)), true);
+ cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
}
/** Unschedule resource event, regardless of its current state. */
case PredictBranch:
{
if (inst->seqNum > cpu->squashSeqNum[tid] &&
- curTick == cpu->lastSquashCycle[tid]) {
+ curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
"skipping prediction \n", tid, inst->seqNum);
} else {
case UpdatePredictor:
{
if (inst->seqNum > cpu->squashSeqNum[tid] &&
- curTick == cpu->lastSquashCycle[tid]) {
+ curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
"skipping branch predictor update \n",
tid, inst->seqNum);
CacheUnit::CachePort::recvAtomic(PacketPtr pkt)
{
panic("CacheUnit::CachePort doesn't expect recvAtomic callback!");
- return curTick;
+ return curTick();
}
void
if (new_slot == -1)
return -1;
- inst->memTime = curTick;
+ inst->memTime = curTick();
setAddrDependency(inst);
return new_slot;
} else {
break;
default:
- panic("%i: Unexpected request type (%i) to %s", curTick,
+ panic("%i: Unexpected request type (%i) to %s", curTick(),
sched_entry->cmd, name());
}
if (secondAddr > addr && !inst->split2ndAccess) {
DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for "
- "(%#x, %#x).\n", curTick, inst->seqNum, addr, secondAddr);
+ "(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr);
// Save All "Total" Split Information
// ==============================
.name(name() + ".predictedNotTakenIncorrect")
.desc("Number of Branches Incorrectly Predicted As Not Taken).");
- lastExecuteCycle = curTick;
+ lastExecuteCycle = curTick();
executions
.name(name() + ".executions")
{
case ExecuteInst:
{
- if (curTick != lastExecuteCycle) {
- lastExecuteCycle = curTick;
+ if (curTick() != lastExecuteCycle) {
+ lastExecuteCycle = curTick();
}
}
if (squashSeqNum[tid] <= done_seq_num &&
- lastSquashCycle[tid] == curTick) {
+ lastSquashCycle[tid] == curTick()) {
DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
"since there is an outstanding squash that is older.\n",
tid, squash_stage);
} else {
squashSeqNum[tid] = done_seq_num;
- lastSquashCycle[tid] = curTick;
+ lastSquashCycle[tid] = curTick();
// If The very next instruction number is the done seq. num,
// then we haven't seen the delay slot yet ... if it isn't
// @TODO: Instructions should never really get to this point since
// this should be handled through the request interface. Check to
// make sure this happens and delete this code.
- if (lastCycleGrad != curTick) {
- lastCycleGrad = curTick;
+ if (lastCycleGrad != curTick()) {
+ lastCycleGrad = curTick();
numCycleGrad = 0;
} else if (numCycleGrad > width) {
DPRINTF(InOrderGraduation,
}
if (inst->traceData) {
- inst->traceData->setStageCycle(stage_num, curTick);
+ inst->traceData->setStageCycle(stage_num, curTick());
}
// Tell CPU that instruction is finished processing
}
}
- if (lastMDUCycle + repeat_rate > curTick) {
+ if (lastMDUCycle + repeat_rate > curTick()) {
DPRINTF(InOrderMDU, "MDU not ready to process another inst. until %i, "
"denying request.\n", lastMDUCycle + repeat_rate);
return -1;
rval);
if (rval != -1) {
- lastMDUCycle = curTick;
+ lastMDUCycle = curTick();
lastOpType = inst->opClass();
lastInstName = inst->staticInst->getName();
}
TrapEvent *trap = new TrapEvent(this, tid);
- cpu->schedule(trap, curTick + trapLatency);
+ cpu->schedule(trap, curTick() + trapLatency);
trapInFlight[tid] = true;
}
// Setup the ROB for whichever stages need it.
commit.setROB(&rob);
- lastRunningCycle = curTick;
+ lastRunningCycle = curTick();
lastActivatedCycle = -1;
#if 0
getState() == SimObject::Drained) {
DPRINTF(O3CPU, "Switched out!\n");
// increment stat
- lastRunningCycle = curTick;
+ lastRunningCycle = curTick();
} else if (!activityRec.active() || _status == Idle) {
DPRINTF(O3CPU, "Idle!\n");
- lastRunningCycle = curTick;
+ lastRunningCycle = curTick();
timesIdled++;
} else {
- schedule(tickEvent, nextCycle(curTick + ticks(1)));
+ schedule(tickEvent, nextCycle(curTick() + ticks(1)));
DPRINTF(O3CPU, "Scheduling next tick!\n");
}
}
// Needs to set each stage to running as well.
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
- "on cycle %d\n", tid, curTick + ticks(delay));
+ "on cycle %d\n", tid, curTick() + ticks(delay));
scheduleActivateThreadEvent(tid, delay);
} else {
activateThread(tid);
}
- if (lastActivatedCycle < curTick) {
+ if (lastActivatedCycle < curTick()) {
scheduleTickEvent(delay);
// Be sure to signal that there's some activity so the CPU doesn't
activityRec.activity();
fetch.wakeFromQuiesce();
- lastActivatedCycle = curTick;
+ lastActivatedCycle = curTick();
_status = Running;
}
// Schedule removal of thread data from CPU
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
- "on cycle %d\n", tid, curTick + ticks(delay));
+ "on cycle %d\n", tid, curTick() + ticks(delay));
scheduleDeallocateContextEvent(tid, remove, delay);
return false;
} else {
DPRINTF(Activity, "Waking up CPU\n");
- idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
- numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
+ idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+ numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
schedule(tickEvent, nextCycle());
}
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
else if (!tickEvent.scheduled())
- schedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
}
/** Unschedule tick event, regardless of its current state. */
// Schedule thread to activate, regardless of its current state.
if (activateThreadEvent[tid].squashed())
reschedule(activateThreadEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
else if (!activateThreadEvent[tid].scheduled())
schedule(activateThreadEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
}
/** Unschedule actiavte thread event, regardless of its current state. */
// Schedule thread to activate, regardless of its current state.
if (deallocateContextEvent[tid].squashed())
reschedule(deallocateContextEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
else if (!deallocateContextEvent[tid].scheduled())
schedule(deallocateContextEvent[tid],
- nextCycle(curTick + ticks(delay)));
+ nextCycle(curTick() + ticks(delay)));
}
/** Unschedule thread deallocation in CPU */
DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
{
panic("DefaultFetch doesn't expect recvAtomic callback!");
- return curTick;
+ return curTick();
}
template<class Impl>
DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
- lastIcacheStall[tid] = curTick;
+ lastIcacheStall[tid] = curTick();
DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
"response.\n", tid);
#if TRACING_ON
if (trace) {
instruction->traceData =
- cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
+ cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
instruction->staticInst, thisPC, curMacroop);
}
#else
FUCompletion *execution = new FUCompletion(issuing_inst,
idx, this);
- cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1));
+ cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1));
// @todo: Enforce that issue_latency == 1 or op_latency
if (issue_latency > 1) {
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
{
panic("O3CPU model does not work with atomic mode!");
- return curTick;
+ return curTick();
}
template <class Impl>
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// @todo: Need to make this a parameter.
- cpu->schedule(wb, curTick);
+ cpu->schedule(wb, curTick());
// Don't need to do anything special for split loads.
if (TheISA::HasUnalignedMemAcc && sreqLow) {
"Instantly completing it.\n",
inst->seqNum);
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
- cpu->schedule(wb, curTick + 1);
+ cpu->schedule(wb, curTick() + 1);
completeStore(storeWBIdx);
incrStIdx(storeWBIdx);
continue;
return;
#if FULL_SYSTEM
- thread->lastActivate = curTick;
+ thread->lastActivate = curTick();
#endif
thread->setStatus(ThreadContext::Active);
return;
#if FULL_SYSTEM
- thread->lastActivate = curTick;
- thread->lastSuspend = curTick;
+ thread->lastActivate = curTick();
+ thread->lastSuspend = curTick();
#endif
/*
#if FULL_SYSTEM
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Read;
memReq->completionEvent = NULL;
- memReq->time = curTick;
+ memReq->time = curTick();
memReq->flags &= ~INST_READ;
MemAccessResult result = dcacheInterface->access(memReq);
--funcExeInst;
memReq->completionEvent = &cacheCompletionEvent;
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
// unscheduleTickEvent();
// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
memReq->cmd = Write;
memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
- memReq->time = curTick;
+ memReq->time = curTick();
memReq->flags &= ~INST_READ;
MemAccessResult result = dcacheInterface->access(memReq);
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
// unscheduleTickEvent();
// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- tickEvent.reschedule(curTick + ticks(delay));
+ tickEvent.reschedule(curTick() + ticks(delay));
else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + ticks(delay));
+ tickEvent.schedule(curTick() + ticks(delay));
}
/// Unschedule tick event, regardless of its current state.
if (tc->status() == ThreadContext::Active &&
_status != Running) {
_status = Running;
- tickEvent.schedule(curTick);
+ tickEvent.schedule(curTick());
}
}
// Nothing running, change status to reflect that we're no longer
comInstEventQueue[0]->serviceEvents(numInst);
if (!tickEvent.scheduled() && _status == Running)
- tickEvent.schedule(curTick + ticks(1));
+ tickEvent.schedule(curTick() + ticks(1));
}
template <class Impl>
FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
{
panic("FrontEnd doesn't expect recvAtomic callback!");
- return curTick;
+ return curTick();
}
template<class Impl>
#if FULL_SYSTEM
if (inst->isQuiesce()) {
-// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
+// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
status = QuiescePending;
break;
}
instruction->staticInst->disassemble(PC));
instruction->traceData =
- Trace::getInstRecord(curTick, tc,
+ Trace::getInstRecord(curTick(), tc,
instruction->staticInst,
instruction->readPC());
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Read;
memReq->completionEvent = NULL;
- memReq->time = curTick;
+ memReq->time = curTick();
MemAccessResult result = dcacheInterface->access(memReq);
// Ugly hack to get an event scheduled *only* if the access is
// Fix this hack for keeping funcExeInst correct with loads that
// are executed twice.
memReq->completionEvent = &cacheCompletionEvent;
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss stall!\n");
memReq->cmd = Write;
// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
- memReq->time = curTick;
+ memReq->time = curTick();
MemAccessResult result = dcacheInterface->access(memReq);
// Ugly hack to get an event scheduled *only* if the access is
// at some point.
if (result != MA_HIT) {
memReq->completionEvent = &cacheCompletionEvent;
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss stall!\n");
// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Read;
req->completionEvent = NULL;
- req->time = curTick;
+ req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
Fault fault = cpu->read(req, data);
// at some point.
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss load stall!\n");
req->cmd = Write;
req->completionEvent = NULL;
- req->time = curTick;
+ req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
memcpy(req->data, (uint8_t *)&data, req->size);
req->data = new uint8_t[64];
memcpy(req->data,(uint8_t *)&data,req->size);
req->completionEvent = NULL;
- req->time = curTick;
+ req->time = curTick();
MemAccessResult result = dcacheInterface->access(req);
// Ugly hack to get an event scheduled *only* if the access is
// at some point.
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss store stall!\n");
FUCompletion *execution = new FUCompletion(issuing_inst,
idx, this);
- execution->schedule(curTick + issue_latency - 1);
+ execution->schedule(curTick() + issue_latency - 1);
} else {
i2e_info->insts[exec_queue_slot++] = issuing_inst;
i2e_info->size++;
req->cmd = Read;
assert(!req->completionEvent);
req->completionEvent = NULL;
- req->time = curTick;
+ req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// FIXME - Need to make this a parameter.
- wb->schedule(curTick);
+ wb->schedule(curTick());
// Should keep track of stat for forwarded data
return NoFault;
// Setup MemReq pointer
req->cmd = Read;
req->completionEvent = NULL;
- req->time = curTick;
+ req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
inst->seqNum);
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
_status = DcacheMissStall;
// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Write;
req->completionEvent = NULL;
- req->time = curTick;
+ req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
req->completionEvent = new
StoreCompletionEvent(storeWBIdx, wb, this);
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
_status = DcacheMissStall;
typename BackEnd::LdWritebackEvent *wb =
new typename BackEnd::LdWritebackEvent(storeQueue[storeWBIdx].inst,
be);
- wb->schedule(curTick);
+ wb->schedule(curTick());
}
completeStore(storeWBIdx);
TrapEvent *trap = new TrapEvent(this);
- trap->schedule(curTick + cpu->ticks(latency));
+ trap->schedule(curTick() + cpu->ticks(latency));
thread->trapPending = true;
}
// Write the done sequence number here.
toIEW->doneSeqNum = inst->seqNum;
- lastCommitCycle = curTick;
+ lastCommitCycle = curTick();
#if FULL_SYSTEM
int count = 0;
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// @todo: Need to make this a parameter.
- wb->schedule(curTick);
+ wb->schedule(curTick());
// Should keep track of stat for forwarded data
return NoFault;
OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
{
panic("O3CPU model does not work with atomic mode!");
- return curTick;
+ return curTick();
}
template <class Impl>
be->addDcacheMiss(inst);
- lastDcacheStall = curTick;
+ lastDcacheStall = curTick();
_status = DcacheMissStall;
const_iterator e = pc_map.end();
for (; i != e; ++i)
- cprintf("%d: event at %#x: %s\n", curTick, (*i)->pc(),
+ cprintf("%d: event at %#x: %s\n", curTick(), (*i)->pc(),
(*i)->descr());
}
numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
//Make sure ticks are still on multiples of cycles
- schedule(tickEvent, nextCycle(curTick + ticks(delay)));
+ schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
_status = Running;
}
latency = ticks(1);
if (_status != Idle)
- schedule(tickEvent, curTick + latency);
+ schedule(tickEvent, curTick() + latency);
}
if(curStaticInst)
{
#if TRACING_ON
- traceData = tracer->getInstRecord(curTick, tc,
+ traceData = tracer->getInstRecord(curTick(), tc,
curStaticInst, thread->pcState(), curMacroStaticInst);
DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
- return curTick;
+ return curTick();
}
void
{
assert(_status == Running || _status == Idle);
_status = SwitchedOut;
- numCycles += tickToCycles(curTick - previousTick);
+ numCycles += tickToCycles(curTick() - previousTick);
// If we've been scheduled to resume but are then told to switch out,
// we'll need to cancel it.
_status = Idle;
}
assert(threadContexts.size() == 1);
- previousTick = curTick;
+ previousTick = curTick();
}
_status = Running;
// kick things off by initiating the fetch of the next instruction
- schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
+ schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
}
if (req->isMmapedIpr()) {
Tick delay;
delay = TheISA::handleIprRead(thread->getTC(), pkt);
- new IprEvent(pkt, this, nextCycle(curTick + delay));
+ new IprEvent(pkt, this, nextCycle(curTick() + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(pkt)) {
{
// fault may be NoFault in cases where a fault is suppressed,
// for instance prefetches.
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ numCycles += tickToCycles(curTick() - previousTick);
+ previousTick = curTick();
if (traceData) {
// Since there was a fault, we shouldn't trace this instruction.
if (req->isMmapedIpr()) {
Tick delay;
delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
- new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
+ new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(dcache_pkt)) {
_status = IcacheWaitResponse;
completeIfetch(NULL);
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ numCycles += tickToCycles(curTick() - previousTick);
+ previousTick = curTick();
}
}
advanceInst(fault);
}
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ numCycles += tickToCycles(curTick() - previousTick);
+ previousTick = curTick();
}
_status = Running;
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ numCycles += tickToCycles(curTick() - previousTick);
+ previousTick = curTick();
if (getState() == SimObject::Draining) {
if (pkt) {
{
if (pkt->isResponse() && !pkt->wasNacked()) {
// delay processing of returned data until next CPU clock edge
- Tick next_tick = cpu->nextCycle(curTick);
+ Tick next_tick = cpu->nextCycle(curTick());
- if (next_tick == curTick)
+ if (next_tick == curTick())
cpu->completeIfetch(pkt);
else
tickEvent.schedule(pkt, next_tick);
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS));
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ numCycles += tickToCycles(curTick() - previousTick);
+ previousTick = curTick();
if (pkt->senderState) {
SplitFragmentSenderState * send_state =
{
if (pkt->isResponse() && !pkt->wasNacked()) {
// delay processing of returned data until next CPU clock edge
- Tick next_tick = cpu->nextCycle(curTick);
+ Tick next_tick = cpu->nextCycle(curTick());
- if (next_tick == curTick) {
+ if (next_tick == curTick()) {
cpu->completeDataAccess(pkt);
} else {
if (!tickEvent.scheduled()) {
if (status() == ThreadContext::Active)
return;
- lastActivate = curTick;
+ lastActivate = curTick();
// if (status() == ThreadContext::Unallocated) {
// cpu->activateWhenReady(_threadId);
if (status() == ThreadContext::Suspended)
return;
- lastActivate = curTick;
- lastSuspend = curTick;
+ lastActivate = curTick();
+ lastSuspend = curTick();
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
void
StaticInst::dumpDecodeCacheStats()
{
- cerr << "Decode hash table stats @ " << curTick << ":" << endl;
+ cerr << "Decode hash table stats @ " << curTick() << ":" << endl;
cerr << "\tnum entries = " << decodeCache.size() << endl;
cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
vector<int> hist(100, 0);
addr);
generator->performCallback(proc, addr);
- schedule(directedStartEvent, curTick);
+ schedule(directedStartEvent, curTick());
}
void
{
if (m_requests_completed < m_requests_to_complete) {
if (!generator->initiate()) {
- schedule(directedStartEvent, curTick + 1);
+ schedule(directedStartEvent, curTick() + 1);
}
} else {
exitSimLoop("Ruby DirectedTester completed");
// must be snoop upcall
assert(pkt->isRequest());
assert(pkt->getDest() == Packet::Broadcast);
- return curTick;
+ return curTick();
}
void
MemTest::CpuPort::recvFunctional(PacketPtr pkt)
{
//Do nothing if we see one come through
-// if (curTick != 0)//Supress warning durring initialization
+// if (curTick() != 0)//Supress warning durring initialization
// warn("Functional Writes not implemented in MemTester\n");
//Need to find any response values that intersect and update
return;
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
panic("%s: read of %x (blk %x) @ cycle %d "
"returns %x, expected %x\n", name(),
- req->getPaddr(), blockAddr(req->getPaddr()), curTick,
+ req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
*pkt_data, *data);
}
if (numReads == (uint64_t)nextProgressMessage) {
ccprintf(cerr, "%s: completed %d read accesses @%d\n",
- name(), numReads, curTick);
+ name(), numReads, curTick());
nextProgressMessage += progressInterval;
}
MemTest::tick()
{
if (!tickEvent.scheduled())
- schedule(tickEvent, curTick + ticks(1));
+ schedule(tickEvent, curTick() + ticks(1));
if (++noResponseCycles >= 500000) {
if (issueDmas) {
cerr << "DMA tester ";
}
- cerr << name() << ": deadlocked at cycle " << curTick << endl;
+ cerr << name() << ": deadlocked at cycle " << curTick() << endl;
fatal("");
}
}
// Prefetches are assumed to be 0 sized
- Request *req = new Request(m_address.getAddress(), 0, flags, curTick,
+ Request *req = new Request(m_address.getAddress(), 0, flags, curTick(),
m_pc.getAddress());
PacketPtr pkt = new Packet(req, cmd, port->idx);
Address writeAddr(m_address.getAddress() + m_store_count);
// Stores are assumed to be 1 byte-sized
- Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick,
+ Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(),
m_pc.getAddress());
Packet::Command cmd;
// Checks are sized depending on the number of bytes written
Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
- curTick, m_pc.getAddress());
+ curTick(), m_pc.getAddress());
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
uint8_t* dataArray = new uint8_t[CHECK_SIZE];
checkForDeadlock();
- schedule(checkStartEvent, curTick + m_wakeup_frequency);
+ schedule(checkStartEvent, curTick() + m_wakeup_frequency);
} else {
exitSimLoop("Ruby Tester completed");
}
int instReqs = 0;
int dataReqs = 0;
- while (nextReq && curTick >= nextCycle) {
+ while (nextReq && curTick() >= nextCycle) {
assert(nextReq->thread_num < 4 && "Not enough threads");
if (nextReq->isInstFetch() && icacheInterface) {
if (icacheInterface->isBlocked())
break;
- nextReq->time = curTick;
+ nextReq->time = curTick();
if (nextReq->cmd == Squash) {
icacheInterface->squash(nextReq->asid);
} else {
break;
++dataReqs;
- nextReq->time = curTick;
+ nextReq->time = curTick();
if (dcacheInterface->doEvents()) {
nextReq->completionEvent =
new TraceCompleteEvent(nextReq, this);
tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
}
} else {
- tickEvent.schedule(max(curTick + ticks(1), nextCycle));
+ tickEvent.schedule(max(curTick() + ticks(1), nextCycle));
}
}
default:
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
sizeof(alphaAccess->cpuStack[0]);
- inform("Launching CPU %d @ %d", cpunum, curTick);
+ inform("Launching CPU %d @ %d", cpunum, curTick());
assert(val > 0 && "Must not access primary cpu");
if (cpunum >= 0 && cpunum < 64)
alphaAccess->cpuStack[cpunum] = val;
DPRINTF(Uart, "TX int enabled, scheduling interruptt\n");
rawInt.txim = 1;
if (!intEvent.scheduled())
- schedule(intEvent, curTick + intDelay);
+ schedule(intEvent, curTick() + intDelay);
}
break;
DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n");
rawInt.txim = 1;
if (!intEvent.scheduled())
- schedule(intEvent, curTick + intDelay);
+ schedule(intEvent, curTick() + intDelay);
}
break;
DPRINTF(Uart, "Data available, scheduling interrupt\n");
if (!intEvent.scheduled())
- schedule(intEvent, curTick + intDelay);
+ schedule(intEvent, curTick() + intDelay);
}
void
startAddr = lcdUpbase;
}
curAddr = 0;
- startTime = curTick;
+ startTime = curTick();
maxAddr = static_cast<Addr>(length*sizeof(uint32_t));
dmaPendingNum =0 ;
DPRINTF(PL111, " -- DMA pending number %d\n", dmaPendingNum);
if (maxAddr == curAddr && !dmaPendingNum) {
- if ((curTick - startTime) > maxFrameTime)
+ if ((curTick() - startTime) > maxFrameTime)
warn("CLCD controller buffer underrun, took %d cycles when should"
- " have taken %d\n", curTick - startTime, maxFrameTime);
+ " have taken %d\n", curTick() - startTime, maxFrameTime);
// double buffering so the vnc server doesn't see a tear in the screen
memcpy(frameBuffer, dmaBuffer, maxAddr);
writeBMP(frameBuffer);
DPRINTF(PL111, "-- schedule next dma read event at %d tick \n",
- maxFrameTime + curTick);
+ maxFrameTime + curTick());
schedule(readEvent, nextCycle(startTime + maxFrameTime));
}
Tick
Pl111::nextCycle()
{
- Tick nextTick = curTick + clock - 1;
+ Tick nextTick = curTick() + clock - 1;
nextTick -= nextTick%clock;
return nextTick;
}
if (nextTick%clock!=0)
nextTick = nextTick - (nextTick%clock) + clock;
- assert(nextTick >= curTick);
+ assert(nextTick >= curTick());
return nextTick;
}
break;
case Clock24:
Tick clk;
- clk = (Tick)(curTick / (24 * SimClock::Float::MHz));
+ clk = (Tick)(curTick() / (24 * SimClock::Float::MHz));
pkt->set((uint32_t)(clk));
break;
case Flash:
DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
zeroEvent.when(), clock, control.timerPrescale);
Tick time;
- time = zeroEvent.when() - curTick;
+ time = zeroEvent.when() - curTick();
time = time / clock / power(16, control.timerPrescale);
DPRINTF(Timer, "-- returning counter at %d\n", time);
pkt->set<uint32_t>(time);
DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
parent->deschedule(zeroEvent);
}
- parent->schedule(zeroEvent, curTick + time);
- DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick + time);
+ parent->schedule(zeroEvent, curTick() + time);
+ DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
}
void
EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
{
if (busy()) {
- DPRINTF(Ethernet, "ethernet packet not sent, bus busy\n", curTick);
+ DPRINTF(Ethernet, "ethernet packet not sent, bus busy\n", curTick());
return false;
}
int delay = (int)ceil(((double)pkt->length * ticksPerByte) + 1.0);
DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n",
delay, ticksPerByte);
- schedule(event, curTick + delay);
+ schedule(event, curTick() + delay);
return true;
}
EtherDump::dumpPacket(EthPacketPtr &packet)
{
pcap_pkthdr pkthdr;
- pkthdr.seconds = curTick / SimClock::Int::s;
- pkthdr.microseconds = (curTick / SimClock::Int::us) % ULL(1000000);
+ pkthdr.seconds = curTick() / SimClock::Int::s;
+ pkthdr.microseconds = (curTick() / SimClock::Int::us) % ULL(1000000);
pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
if (linkDelay > 0) {
DPRINTF(Ethernet, "packet delayed: delay=%d\n", linkDelay);
Event *event = new LinkDelayEvent(this, packet);
- parent->schedule(event, curTick + linkDelay);
+ parent->schedule(event, curTick() + linkDelay);
} else {
txComplete(packet);
}
DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n",
delay, ticksPerByte);
- parent->schedule(doneEvent, curTick + delay);
+ parent->schedule(doneEvent, curTick() + delay);
return true;
}
DPRINTF(Ethernet, "bus busy...buffer for retransmission\n");
packetBuffer.push(packet);
if (!txEvent.scheduled())
- schedule(txEvent, curTick + retryTime);
+ schedule(txEvent, curTick() + retryTime);
} else if (dump) {
dump->dump(packet);
}
}
if (!packetBuffer.empty() && !txEvent.scheduled())
- schedule(txEvent, curTick + retryTime);
+ schedule(txEvent, curTick() + retryTime);
}
EtherInt*
Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
DPRINTF(EthernetIntr,
- "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
- curTick, regs.itr.interval(), itr_interval);
+ "EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
+ curTick(), regs.itr.interval(), itr_interval);
if (regs.itr.interval() == 0 || now ||
- lastInterrupt + itr_interval <= curTick) {
+ lastInterrupt + itr_interval <= curTick()) {
if (interEvent.scheduled()) {
deschedule(interEvent);
}
intrPost();
- lastInterrupt = curTick;
+ lastInterrupt = curTick();
}
void
DPRINTF(Ethernet,
"Possibly scheduling interrupt because of imr write\n");
if (!interEvent.scheduled()) {
- Tick t = curTick + SimClock::Int::ns * 256 * regs.itr.interval();
+ Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
DPRINTF(Ethernet, "Scheduling for %d\n", t);
schedule(interEvent, t);
}
wbOut = max_to_wb;
assert(!wbDelayEvent.scheduled());
- igbe->schedule(wbDelayEvent, curTick + igbe->wbDelay);
+ igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
igbe->anBegin(annSmWb, "Prepare Writeback Desc");
}
{
// If we're draining delay issuing this DMA
if (igbe->getState() != SimObject::Running) {
- igbe->schedule(wbDelayEvent, curTick + igbe->wbDelay);
+ igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
return;
}
curFetching = max_to_fetch;
assert(!fetchDelayEvent.scheduled());
- igbe->schedule(fetchDelayEvent, curTick + igbe->fetchDelay);
+ igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
}
{
// If we're draining delay issuing this DMA
if (igbe->getState() != SimObject::Running) {
- igbe->schedule(fetchDelayEvent, curTick + igbe->fetchDelay);
+ igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
return;
}
if (igbe->regs.rdtr.delay()) {
Tick delay = igbe->regs.rdtr.delay() * igbe->intClock();
DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay);
- igbe->reschedule(igbe->rdtrEvent, curTick + delay);
+ igbe->reschedule(igbe->rdtrEvent, curTick() + delay);
}
if (igbe->regs.radv.idv()) {
Tick delay = igbe->regs.radv.idv() * igbe->intClock();
DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay);
if (!igbe->radvEvent.scheduled()) {
- igbe->schedule(igbe->radvEvent, curTick + delay);
+ igbe->schedule(igbe->radvEvent, curTick() + delay);
}
}
if (igbe->regs.tidv.idv()) {
Tick delay = igbe->regs.tidv.idv() * igbe->intClock();
DPRINTF(EthernetDesc, "setting tidv\n");
- igbe->reschedule(igbe->tidvEvent, curTick + delay, true);
+ igbe->reschedule(igbe->tidvEvent, curTick() + delay, true);
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
Tick delay = igbe->regs.tadv.idv() * igbe->intClock();
DPRINTF(EthernetDesc, "setting tadv\n");
if (!igbe->tadvEvent.scheduled()) {
- igbe->schedule(igbe->tadvEvent, curTick + delay);
+ igbe->schedule(igbe->tadvEvent, curTick() + delay);
}
}
}
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
getState() == SimObject::Running)
- schedule(tickEvent, (curTick / ticks(1)) * ticks(1) + ticks(1));
+ schedule(tickEvent, (curTick() / ticks(1)) * ticks(1) + ticks(1));
}
unsigned int
if (rxTick || txTick || txFifoTick)
- schedule(tickEvent, curTick + ticks(1));
+ schedule(tickEvent, curTick() + ticks(1));
}
void
dmaState, devState);
if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
- schedule(dmaTransferEvent, curTick + DMA_BACKOFF_PERIOD);
+ schedule(dmaTransferEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else
ctrl->dmaRead(curPrdAddr, sizeof(PrdEntry_t), &dmaPrdReadEvent,
DPRINTF(IdeDisk, "doDmaRead, diskDelay: %d totalDiskDelay: %d\n",
diskDelay, totalDiskDelay);
- schedule(dmaReadWaitEvent, curTick + totalDiskDelay);
+ schedule(dmaReadWaitEvent, curTick() + totalDiskDelay);
}
void
}
if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
- schedule(dmaReadWaitEvent, curTick + DMA_BACKOFF_PERIOD);
+ schedule(dmaReadWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaReadCG->done()) {
assert(dmaReadCG->complete() < MAX_DMA_SIZE);
cmdBytesLeft -= SectorSize;
}
- schedule(dmaWriteWaitEvent, curTick + totalDiskDelay);
+ schedule(dmaWriteWaitEvent, curTick() + totalDiskDelay);
}
void
curPrd.getByteCount(), TheISA::PageBytes);
}
if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
- schedule(dmaWriteWaitEvent, curTick + DMA_BACKOFF_PERIOD);
+ schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaWriteCG->done()) {
assert(dmaWriteCG->complete() < MAX_DMA_SIZE);
dmaState = Dma_Transfer;
// schedule dma transfer (doDmaTransfer)
- schedule(dmaTransferEvent, curTick + 1);
+ schedule(dmaTransferEvent, curTick() + 1);
}
void
{
if (clocks == 0)
panic("Timer can't be set to go off instantly.\n");
- DPRINTF(Intel8254Timer, "Timer set to curTick + %d\n",
+ DPRINTF(Intel8254Timer, "Timer set to curTick() + %d\n",
clocks * interval);
- counter->parent->schedule(this, curTick + clocks * interval);
+ counter->parent->schedule(this, curTick() + clocks * interval);
}
int
{
if (!scheduled())
return -1;
- return (when() - curTick + interval - 1) / interval;
+ return (when() - curTick() + interval - 1) / interval;
}
const char *
else if (backoffTime < maxBackoffDelay)
backoffTime <<= 1;
- reschedule(backoffEvent, curTick + backoffTime, true);
+ reschedule(backoffEvent, curTick() + backoffTime, true);
DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime);
if (state->totBytes == state->numBytes) {
if (state->completionEvent) {
if (state->delay)
- schedule(state->completionEvent, curTick + state->delay);
+ schedule(state->completionEvent, curTick() + state->delay);
else
state->completionEvent->process();
}
} while (!backoffTime && result && transmitList.size());
if (transmitList.size() && backoffTime && !inRetry) {
- DPRINTF(DMA, "Scheduling backoff for %d\n", curTick+backoffTime);
+ DPRINTF(DMA, "Scheduling backoff for %d\n", curTick()+backoffTime);
if (!backoffEvent.scheduled())
- schedule(backoffEvent, backoffTime + curTick);
+ schedule(backoffEvent, backoffTime + curTick());
}
DPRINTF(DMA, "TransmitList: %d, backoffTime: %d inRetry: %d es: %d\n",
transmitList.size(), backoffTime, inRetry,
if (transmitList.size() && backoffTime && !inRetry &&
!backoffEvent.scheduled()) {
DPRINTF(DMA, "-- Scheduling backoff timer for %d\n",
- backoffTime+curTick);
- schedule(backoffEvent, backoffTime + curTick);
+ backoffTime+curTick());
+ schedule(backoffEvent, backoffTime + curTick());
}
} else if (state == Enums::atomic) {
transmitList.pop_front();
if (state->totBytes == state->numBytes) {
if (state->completionEvent) {
assert(!state->completionEvent->scheduled());
- schedule(state->completionEvent, curTick + lat + state->delay);
+ schedule(state->completionEvent, curTick() + lat + state->delay);
}
delete state;
delete pkt->req;
// save the timer tick and rtc clock tick values to correctly reschedule
// them during unserialize
//
- Tick rtcTimerInterruptTickOffset = event.when() - curTick;
+ Tick rtcTimerInterruptTickOffset = event.when() - curTick();
SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
- Tick rtcClockTickOffset = event.when() - curTick;
+ Tick rtcClockTickOffset = event.when() - curTick();
SERIALIZE_SCALAR(rtcClockTickOffset);
}
//
Tick rtcTimerInterruptTickOffset;
UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
- reschedule(event, curTick + rtcTimerInterruptTickOffset);
+ reschedule(event, curTick() + rtcTimerInterruptTickOffset);
Tick rtcClockTickOffset;
UNSERIALIZE_SCALAR(rtcClockTickOffset);
- reschedule(tickEvent, curTick + rtcClockTickOffset);
+ reschedule(tickEvent, curTick() + rtcClockTickOffset);
}
MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
: parent(_parent), interval(i)
{
DPRINTF(MC146818, "RTC Event Initilizing\n");
- parent->schedule(this, curTick + interval);
+ parent->schedule(this, curTick() + interval);
}
void
MC146818::RTCEvent::scheduleIntr()
{
- parent->schedule(this, curTick + interval);
+ parent->schedule(this, curTick() + interval);
}
void
MC146818::RTCEvent::process()
{
DPRINTF(MC146818, "RTC Timer Interrupt\n");
- parent->schedule(this, curTick + interval);
+ parent->schedule(this, curTick() + interval);
parent->handleEvent();
}
MC146818::RTCTickEvent::process()
{
DPRINTF(MC146818, "RTC clock tick\n");
- parent->schedule(this, curTick + SimClock::Int::s);
+ parent->schedule(this, curTick() + SimClock::Int::s);
parent->tickClock();
}
RTCTickEvent(MC146818 * _parent) : parent(_parent)
{
- parent->schedule(this, curTick + SimClock::Int::s);
+ parent->schedule(this, curTick() + SimClock::Int::s);
}
/** Event process to occur at interrupt*/
interrupts, regs.isr, regs.imr);
if ((regs.isr & regs.imr)) {
- Tick when = curTick;
+ Tick when = curTick();
if ((regs.isr & regs.imr & ISR_NODELAY) == 0)
when += intrDelay;
postedInterrupts++;
regs.isr, regs.imr, regs.isr & regs.imr);
if (regs.isr & regs.imr)
- cpuIntrPost(curTick);
+ cpuIntrPost(curTick());
else
cpuIntrClear();
}
* @todo this warning should be removed and the intrTick code should
* be fixed.
*/
- assert(when >= curTick);
- assert(intrTick >= curTick || intrTick == 0);
+ assert(when >= curTick());
+ assert(intrTick >= curTick() || intrTick == 0);
if (when > intrTick && intrTick != 0) {
DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n",
intrTick);
}
intrTick = when;
- if (intrTick < curTick) {
+ if (intrTick < curTick()) {
debug_break();
- intrTick = curTick;
+ intrTick = curTick();
}
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
void
NSGigE::cpuInterrupt()
{
- assert(intrTick == curTick);
+ assert(intrTick == curTick());
// Whether or not there's a pending interrupt, we don't care about
// it anymore
next:
if (clock) {
- if (rxKickTick > curTick) {
+ if (rxKickTick > curTick()) {
DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
rxKickTick);
}
// Go to the next state machine clock tick.
- rxKickTick = curTick + ticks(1);
+ rxKickTick = curTick() + ticks(1);
}
switch(rxDmaState) {
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
- schedule(txEvent, curTick + retryTime);
+ schedule(txEvent, curTick() + retryTime);
}
}
next:
if (clock) {
- if (txKickTick > curTick) {
+ if (txKickTick > curTick()) {
DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
txKickTick);
goto exit;
}
// Go to the next state machine clock tick.
- txKickTick = curTick + ticks(1);
+ txKickTick = curTick() + ticks(1);
}
switch(txDmaState) {
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- reschedule(txEvent, curTick + ticks(1), true);
+ reschedule(txEvent, curTick() + ticks(1), true);
}
bool
* If there's a pending transmit, store the time so we can
* reschedule it later
*/
- Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
+ Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
SERIALIZE_SCALAR(transmitTick);
/*
Tick transmitTick;
UNSERIALIZE_SCALAR(transmitTick);
if (transmitTick)
- schedule(txEvent, curTick + transmitTick);
+ schedule(txEvent, curTick() + transmitTick);
/*
* unserialize receive address filter settings
interrupts &= ~Regs::Intr_TxLow;
if (interrupts) {
- Tick when = curTick;
+ Tick when = curTick();
if ((interrupts & Regs::Intr_NoDelay) == 0)
when += intrDelay;
cpuIntrPost(when);
regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
if (regs.IntrStatus & regs.IntrMask)
- cpuIntrPost(curTick);
+ cpuIntrPost(curTick());
else
cpuIntrClear();
}
* @todo this warning should be removed and the intrTick code should
* be fixed.
*/
- assert(when >= curTick);
- assert(intrTick >= curTick || intrTick == 0);
+ assert(when >= curTick());
+ assert(intrTick >= curTick() || intrTick == 0);
if (!cpuIntrEnable) {
DPRINTF(EthernetIntr, "interrupts not enabled.\n",
intrTick);
}
intrTick = when;
- if (intrTick < curTick) {
+ if (intrTick < curTick()) {
debug_break();
- intrTick = curTick;
+ intrTick = curTick();
}
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
void
Base::cpuInterrupt()
{
- assert(intrTick == curTick);
+ assert(intrTick == curTick());
// Whether or not there's a pending interrupt, we don't care about
// it anymore
cpuIntrEnable = regs.Config & Regs::Config_IntEn;
if (cpuIntrEnable) {
if (regs.IntrStatus & regs.IntrMask)
- cpuIntrPost(curTick);
+ cpuIntrPost(curTick());
} else {
cpuIntrClear();
}
DPRINTF(EthernetSM, "rxKick: rxState=%s (rxFifo.size=%d)\n",
RxStateStrings[rxState], rxFifo.size());
- if (rxKickTick > curTick) {
+ if (rxKickTick > curTick()) {
DPRINTF(EthernetSM, "rxKick: exiting, can't run till %d\n",
rxKickTick);
return;
DPRINTF(EthernetSM, "txKick: txState=%s (txFifo.size=%d)\n",
TxStateStrings[txState], txFifo.size());
- if (txKickTick > curTick) {
+ if (txKickTick > curTick()) {
DPRINTF(EthernetSM, "txKick: exiting, can't run till %d\n",
txKickTick);
return;
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- reschedule(txEvent, curTick + ticks(1), true);
+ reschedule(txEvent, curTick() + ticks(1), true);
}
bool
* If there's a pending transmit, store the time so we can
* reschedule it later
*/
- Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
+ Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
SERIALIZE_SCALAR(transmitTick);
}
Tick transmitTick;
UNSERIALIZE_SCALAR(transmitTick);
if (transmitTick)
- schedule(txEvent, curTick + transmitTick);
+ schedule(txEvent, curTick() + transmitTick);
pioPort->sendStatusChange(Port::RangeChange);
DPRINTF(Uart, "UART InterEvent, interrupting\n");
uart->platform->postConsoleInt();
uart->status |= intrBit;
- uart->lastTxInt = curTick;
+ uart->lastTxInt = curTick();
}
else
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
{
static const Tick interval = 225 * SimClock::Int::ns;
DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
- curTick + interval);
+ curTick() + interval);
if (!scheduled())
- uart->schedule(this, curTick + interval);
+ uart->schedule(this, curTick() + interval);
else
- uart->reschedule(this, curTick + interval);
+ uart->reschedule(this, curTick() + interval);
}
if (UART_IER_THRI & IER)
{
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
- if (curTick - lastTxInt > 225 * SimClock::Int::ns) {
+ if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
- curTick, lastTxInt);
+ curTick(), lastTxInt);
txIntrEvent.process();
} else {
DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
- curTick, lastTxInt);
+ curTick(), lastTxInt);
txIntrEvent.scheduleIntr();
}
}
return;
_iplGood[ipl]++;
- _iplTicks[iplLast] += curTick - iplLastTick;
- iplLastTick = curTick;
+ _iplTicks[iplLast] += curTick() - iplLastTick;
+ iplLastTick = curTick();
iplLast = ipl;
}
pkt->setNacked();
//put it on the list to send
- Tick readyTime = curTick + nackDelay;
+ Tick readyTime = curTick() + nackDelay;
PacketBuffer *buf = new PacketBuffer(pkt, readyTime, true);
// nothing on the list, add it and we're done
- Tick readyTime = curTick + delay;
+ Tick readyTime = curTick() + delay;
PacketBuffer *buf = new PacketBuffer(pkt, readyTime);
// If we're about to put this packet at the head of the queue, we
PacketBuffer *buf = sendQueue.front();
- assert(buf->ready <= curTick);
+ assert(buf->ready <= curTick());
PacketPtr pkt = buf->pkt;
if (!sendQueue.empty()) {
buf = sendQueue.front();
DPRINTF(BusBridge, "Scheduling next send\n");
- schedule(sendEvent, std::max(buf->ready, curTick + 1));
+ schedule(sendEvent, std::max(buf->ready, curTick() + 1));
}
} else {
DPRINTF(BusBridge, " unsuccessful\n");
{
inRetry = false;
Tick nextReady = sendQueue.front()->ready;
- if (nextReady <= curTick)
+ if (nextReady <= curTick())
trySend();
else
schedule(sendEvent, nextReady);
// a cycle boundary to take up only the following cycle. Anything
// that happens later will have to "wait" for the end of that
// cycle, and then start using the bus after that.
- if (tickNextIdle < curTick) {
- tickNextIdle = curTick;
+ if (tickNextIdle < curTick()) {
+ tickNextIdle = curTick();
if (tickNextIdle % clock != 0)
- tickNextIdle = curTick - (curTick % clock) + clock;
+ tickNextIdle = curTick() - (curTick() % clock) + clock;
}
Tick headerTime = tickNextIdle + headerCycles * clock;
reschedule(busIdle, tickNextIdle, true);
DPRINTF(Bus, "The bus is now occupied from tick %d to %d\n",
- curTick, tickNextIdle);
+ curTick(), tickNextIdle);
}
/** Function called by the port when the bus is receiving a Timing
// If the bus is busy, or other devices are in line ahead of the current
// one, put this device on the retry list.
if (!pkt->isExpressSnoop() &&
- (tickNextIdle > curTick ||
+ (tickNextIdle > curTick() ||
(retryList.size() && (!inRetry || src_port != retryList.front()))))
{
addToRetryList(src_port);
Bus::recvRetry(int id)
{
// If there's anything waiting, and the bus isn't busy...
- if (retryList.size() && curTick >= tickNextIdle) {
+ if (retryList.size() && curTick() >= tickNextIdle) {
//retryingPort = retryList.front();
inRetry = true;
DPRINTF(Bus, "Sending a retry to %s\n", retryList.front()->getPeer()->name());
inRetry = false;
//Bring tickNextIdle up to the present
- while (tickNextIdle < curTick)
+ while (tickNextIdle < curTick())
tickNextIdle += clock;
//Burn a cycle for the missed grant.
}
}
//If we weren't able to drain before, we might be able to now.
- if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) {
+ if (drainEvent && retryList.size() == 0 && curTick() >= tickNextIdle) {
drainEvent->process();
// Clear the drain event once we're done with it.
drainEvent = NULL;
}
// why do we have this packet field and the return value both???
- pkt->finishTime = curTick + response_latency;
+ pkt->finishTime = curTick() + response_latency;
return response_latency;
}
//We should check that we're not "doing" anything, and that noone is
//waiting. We might be idle but have someone waiting if the device we
//contacted for a retry didn't actually retry.
- if (retryList.size() || (curTick < tickNextIdle && busIdle.scheduled())) {
+ if (retryList.size() || (curTick() < tickNextIdle && busIdle.scheduled())) {
drainEvent = de;
return 1;
}
void
Bus::startup()
{
- if (tickNextIdle < curTick)
- tickNextIdle = (curTick / clock) * clock + clock;
+ if (tickNextIdle < curTick())
+ tickNextIdle = (curTick() / clock) * clock + clock;
}
Bus *
mustSendRetry = false;
SendRetryEvent *ev = new SendRetryEvent(this, true);
// @TODO: need to find a better time (next bus cycle?)
- schedule(ev, curTick + 1);
+ schedule(ev, curTick() + 1);
}
}
uint8_t flag = 1 << cause;
if (blocked == 0) {
blocked_causes[cause]++;
- blockedCycle = curTick;
+ blockedCycle = curTick();
cpuSidePort->setBlocked();
}
blocked |= flag;
blocked &= ~flag;
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
- blocked_cycles[cause] += curTick - blockedCycle;
+ blocked_cycles[cause] += curTick() - blockedCycle;
cpuSidePort->clearBlocked();
}
}
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
- /** Which curTick will this block be accessable */
+ /** Which curTick() will this block be accessable */
Tick whenReady;
/**
// MemDebug::cacheAccess(pkt);
// we charge hitLatency for doing just about anything here
- Tick time = curTick + hitLatency;
+ Tick time = curTick() + hitLatency;
if (pkt->isResponse()) {
// must be cache-to-cache response from upper to lower level
if (satisfied) {
if (needsResponse) {
pkt->makeTimingResponse();
- cpuSidePort->respond(pkt, curTick+lat);
+ cpuSidePort->respond(pkt, curTick()+lat);
} else {
delete pkt;
}
noTargetMSHR = mshr;
setBlocked(Blocked_NoTargets);
// need to be careful with this... if this mshr isn't
- // ready yet (i.e. time > curTick_, we don't want to
+ // ready yet (i.e. time > curTick()_, we don't want to
// move it ahead of mshrs that are ready
// mshrQueue.moveToFront(mshr);
}
void
Cache<TagStore>::handleResponse(PacketPtr pkt)
{
- Tick time = curTick + hitLatency;
+ Tick time = curTick() + hitLatency;
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
bool is_error = pkt->isError();
MSHR::Target *initial_tgt = mshr->getTarget();
BlkType *blk = tags->findBlock(pkt->getAddr());
int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
- Tick miss_latency = curTick - initial_tgt->recvTime;
+ Tick miss_latency = curTick() - initial_tgt->recvTime;
PacketList writebacks;
if (pkt->req->isUncacheable()) {
// invalidate it.
pkt->cmd = MemCmd::ReadRespWithInvalidate;
}
- memSidePort->respond(pkt, curTick + hitLatency);
+ memSidePort->respond(pkt, curTick() + hitLatency);
}
template<class TagStore>
// (hwpf_mshr_misses)
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
// Don't request bus, since we already have it
- return allocateMissBuffer(pkt, curTick, false);
+ return allocateMissBuffer(pkt, curTick(), false);
}
}
}
pkt = new Packet(tgt_pkt);
pkt->cmd = MemCmd::UpgradeFailResp;
pkt->senderState = mshr;
- pkt->firstWordTime = pkt->finishTime = curTick;
+ pkt->firstWordTime = pkt->finishTime = curTick();
handleResponse(pkt);
return NULL;
} else if (mshr->isForwardNoResponse()) {
// @TODO: need to facotr in prefetch requests here somehow
if (nextReady != MaxTick) {
DPRINTF(CachePort, "more packets to send @ %d\n", nextReady);
- schedule(sendEvent, std::max(nextReady, curTick + 1));
+ schedule(sendEvent, std::max(nextReady, curTick() + 1));
} else {
// no more to send right now: if we're draining, we may be done
if (drainEvent && !sendEvent->scheduled()) {
// Actual target device (typ. PhysicalMemory) will delete the
// packet on reception, so we need to save a copy here.
PacketPtr cp_pkt = new Packet(pkt, true);
- targets->add(cp_pkt, curTick, _order, Target::FromSnoop,
+ targets->add(cp_pkt, curTick(), _order, Target::FromSnoop,
downstreamPending && targets->needsExclusive);
++ntargets;
deferredTargets->resetFlags();
order = targets->front().order;
- readyTime = std::max(curTick, targets->front().readyTime);
+ readyTime = std::max(curTick(), targets->front().readyTime);
return true;
}
Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
Source _source, bool _markedPending)
- : recvTime(curTick), readyTime(_readyTime), order(_order),
+ : recvTime(curTick()), readyTime(_readyTime), order(_order),
pkt(_pkt), source(_source), markedPending(_markedPending)
{}
};
*/
MSHR *getNextMSHR() const
{
- if (readyList.empty() || readyList.front()->readyTime > curTick) {
+ if (readyList.empty() || readyList.front()->readyTime > curTick()) {
return NULL;
}
return readyList.front();
blk->isTouched = true;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
- warmupCycle = curTick;
+ warmupCycle = curTick();
}
}
//assert(check());
hitDepthTotal += sets[set].depth;
tag_ptr->status |= BlkReferenced;
lat = set_lat;
- if (tag_ptr->whenReady > curTick && tag_ptr->whenReady - curTick > set_lat) {
- lat = tag_ptr->whenReady - curTick;
+ if (tag_ptr->whenReady > curTick() && tag_ptr->whenReady - curTick() > set_lat) {
+ lat = tag_ptr->whenReady - curTick();
}
tag_ptr->refCount += 1;
tagsInUse++;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
- warmupCycle = curTick;
+ warmupCycle = curTick();
}
return tag_ptr;
sets[set].moveToHead(blk);
DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
set, regenerateBlkAddr(tag, set));
- if (blk->whenReady > curTick
- && blk->whenReady - curTick > hitLatency) {
- lat = blk->whenReady - curTick;
+ if (blk->whenReady > curTick()
+ && blk->whenReady - curTick() > hitLatency) {
+ lat = blk->whenReady - curTick();
}
blk->refCount += 1;
}
blk->isTouched = true;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
- warmupCycle = curTick;
+ warmupCycle = curTick();
}
}
int SD_BEST_T_WRITE_READ_OBANK = (war_lat -1); /* WAR, row miss/hit, another bank */
int SD_BEST_T_WRITE_WRITE_OBANK = 0; /* WAW, row miss/hit, another bank */
- Tick time_since_last_access = curTick-time_last_access;
+ Tick time_since_last_access = curTick()-time_last_access;
Tick time_last_miss = 0; // used for keeping track of times between activations (page misses)
- //int was_idle = (curTick > busy_until);
+ //int was_idle = (curTick() > busy_until);
bool srow_flag = false;
int timing_correction = 0;
- int was_idle = (curTick > busy_until[current_bank]);
- cycles_nCKE[0] += was_idle ? MIN(curTick-busy_until[current_bank], time_since_last_access) : 0;
+ int was_idle = (curTick() > busy_until[current_bank]);
+ cycles_nCKE[0] += was_idle ? MIN(curTick()-busy_until[current_bank], time_since_last_access) : 0;
// bank is precharged
//active_row[current_bank] == DR_NUM_ROWS
if(all_precharged) {
if(was_idle) {
- cycles_all_precharge_nCKE[0] += MIN(curTick-busy_until[current_bank], time_since_last_access);
+ cycles_all_precharge_nCKE[0] += MIN(curTick()-busy_until[current_bank], time_since_last_access);
cycles_all_precharge_CKE[0] += MIN(0, busy_until[current_bank]-time_last_access);
}
else {
}
} else { // some bank is active
if(was_idle) {
- cycles_bank_active_nCKE[0] += MIN(curTick-busy_until[current_bank], time_since_last_access);
+ cycles_bank_active_nCKE[0] += MIN(curTick()-busy_until[current_bank], time_since_last_access);
}
else {
}
}
- time_last_access = curTick;
+ time_last_access = curTick();
////////////////////////////////////////////////////////////////////////////
if ((mem_type == "SDRAM") && (mem_actpolicy == "open"))
if (memctrlpipe_enable == true)
{
- overlap=(int)(busy_until[current_bank] - curTick);
+ overlap=(int)(busy_until[current_bank] - curTick());
}
else overlap = 0;
corrected_overlap = (int) (overlap/cpu_ratio);
}
- /*fprintf(stderr,"%10.0f %10.0f %4d %4d ",(double)busy_until, (double)curTick, overlap, corrected_overlap); debugging*/
+ /*fprintf(stderr,"%10.0f %10.0f %4d %4d ",(double)busy_until, (double)curTick(), overlap, corrected_overlap); debugging*/
if (cmdIsRead == lastCmdIsRead)/*same command*/
{
{
if (memctrlpipe_enable == true)
{
- busy_until[current_bank]=curTick+lat+
+ busy_until[current_bank]=curTick()+lat+
timing_correction;
}
else
{
- if (busy_until[current_bank] >= curTick)
+ if (busy_until[current_bank] >= curTick())
{
busy_until[current_bank]+=(lat+
timing_correction);
total_arb_latency += (busy_until[current_bank]
- - curTick - lat
+ - curTick() - lat
- timing_correction);
- lat=busy_until[current_bank] - curTick;
+ lat=busy_until[current_bank] - curTick();
}
- else busy_until[current_bank]=curTick+lat+
+ else busy_until[current_bank]=curTick()+lat+
timing_correction;
}
}
- else/*the memory request will be satisfied temp cycles after curTick*/
+ else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=(lat+
timing_correction);
if (memctrlpipe_enable == true)
{
- overlap=(int)(busy_until[current_bank] - curTick);
+ overlap=(int)(busy_until[current_bank] - curTick());
}
else overlap=0;
corrected_overlap = (int) (overlap/cpu_ratio);
}
- /*fprintf(stderr,"%10.0f %10.0f %6d %6d %2d %2d ",(double)busy_until, (double)curTick, overlap, corrected_overlap,precharge,adjacent);debugging*/
+ /*fprintf(stderr,"%10.0f %10.0f %6d %6d %2d %2d ",(double)busy_until, (double)curTick(), overlap, corrected_overlap,precharge,adjacent);debugging*/
if (cmdIsRead == lastCmdIsRead)/*same command*/
{
{
if (memctrlpipe_enable == true)
{
- busy_until[current_bank] =curTick+lat;
+ busy_until[current_bank] =curTick()+lat;
}
else
{
- if (busy_until[current_bank] >= curTick)
+ if (busy_until[current_bank] >= curTick())
{
busy_until[current_bank] +=lat;
- lat=busy_until[current_bank] - curTick;
+ lat=busy_until[current_bank] - curTick();
}
- else busy_until[current_bank] = curTick+lat;
+ else busy_until[current_bank] = curTick()+lat;
}
}
- else/*the memory request will be satisfied temp cycles after curTick*/
+ else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
}
total_access++;
- overlap=(int)(busy_until[current_bank] - curTick);
+ overlap=(int)(busy_until[current_bank] - curTick());
if (current_bank == last_bank)/*same bank*/
{
if (overlap <= 0) /*memory interface is not busy*/
{
- busy_until[current_bank] = curTick+lat;
+ busy_until[current_bank] = curTick()+lat;
}
- else /*the memory request will be satisfied temp cycles after curTick*/
+ else /*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
- /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);debug*/
+ /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick(), overlap, lat);debug*/
// if((_cpu_num < num_cpus) && (_cpu_num >= 0))
// cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
// bank_access_profile[_cpu_num][current_bank]++;
}
total_access++;
- overlap=(int)(busy_until[current_bank] - curTick);
+ overlap=(int)(busy_until[current_bank] - curTick());
if (cpu_ratio < 1.0)
{
if (overlap <= 0) /*memory interface is not busy*/
{
- busy_until[current_bank] = curTick+lat;
+ busy_until[current_bank] = curTick()+lat;
}
- else/*the memory request will be satisfied temp cycles after curTick*/
+ else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
lat+=overlap;
}
- /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);*/
+ /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick(), overlap, lat);*/
if (cmdIsRead)
{
total_access++;
lat += chunks;
- overlap=(int)(busy_until[current_bank] - curTick);
+ overlap=(int)(busy_until[current_bank] - curTick());
lastCmdIsRead=cmdIsRead;
if (cpu_ratio < 1.0)
if (overlap <= 0) /*memory interface is not busy*/
{
- busy_until[current_bank] = curTick+lat;
+ busy_until[current_bank] = curTick()+lat;
}
- else/*the memory request will be satisfied temp cycles after curTick*/
+ else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; /* DR_T_RP + */
}
total_access++;
- overlap=(int)(busy_until[current_bank] - curTick);
+ overlap=(int)(busy_until[current_bank] - curTick());
lat += chunks * DR_T_PACKET; /*every 128 bit need DR_NUM_CYCLES*/
if (cpu_ratio < 1.0)
if (overlap <= 0) /*memory interface is not busy*/
{
- busy_until[current_bank] = curTick+lat;
+ busy_until[current_bank] = curTick()+lat;
}
- else/*the memory request will be satisfied temp cycles after curTick*/
+ else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] += lat;
command_overlapping++;
void
MessagePort::sendMessageTiming(PacketPtr pkt, Tick latency)
{
- schedSendTiming(pkt, curTick + latency);
+ schedSendTiming(pkt, curTick() + latency);
}
Tick
*/
Packet(Request *_req, MemCmd _cmd, NodeID _dest)
: flags(VALID_DST), cmd(_cmd), req(_req), data(NULL),
- dest(_dest), time(curTick), senderState(NULL)
+ dest(_dest), time(curTick()), senderState(NULL)
{
if (req->hasPaddr()) {
addr = req->getPaddr();
*/
Packet(Request *_req, MemCmd _cmd, NodeID _dest, int _blkSize)
: flags(VALID_DST), cmd(_cmd), req(_req), data(NULL),
- dest(_dest), time(curTick), senderState(NULL)
+ dest(_dest), time(curTick()), senderState(NULL)
{
if (req->hasPaddr()) {
addr = req->getPaddr() & ~(_blkSize - 1);
: cmd(pkt->cmd), req(pkt->req),
data(pkt->flags.isSet(STATIC_DATA) ? pkt->data : NULL),
addr(pkt->addr), size(pkt->size), src(pkt->src), dest(pkt->dest),
- time(curTick), senderState(pkt->senderState)
+ time(curTick()), senderState(pkt->senderState)
{
if (!clearFlags)
flags.set(pkt->flags & COPY_FLAGS);
/**
* The time this request was started. Used to calculate
- * latencies. This field is set to curTick any time paddr or vaddr
+ * latencies. This field is set to curTick() any time paddr or vaddr
* is written.
*/
Tick _time;
/**
* Constructor for physical (e.g. device) requests. Initializes
- * just physical address, size, flags, and timestamp (to curTick).
+ * just physical address, size, flags, and timestamp (to curTick()).
* These fields are adequate to perform a request.
*/
Request(Addr paddr, int size, Flags flags)
void
setPhys(Addr paddr, int size, Flags flags)
{
- setPhys(paddr, size, flags, curTick);
+ setPhys(paddr, size, flags, curTick());
}
/**
_vaddr = vaddr;
_size = size;
_pc = pc;
- _time = curTick;
+ _time = curTick();
_flags.clear(~STICKY_FLAGS);
_flags.set(flags);
RubyEventQueue(EventQueue* eventq, Tick _clock);
~RubyEventQueue();
- Time getTime() const { return curTick/m_clock; }
+ Time getTime() const { return curTick()/m_clock; }
Tick getClock() const { return m_clock; }
void scheduleEvent(Consumer* consumer, Time timeDelta);
void scheduleEventAbsolute(Consumer* consumer, Time timeAbs);
RubyPort::M5Port::sendTiming(PacketPtr pkt)
{
//minimum latency, must be > 0
- schedSendTiming(pkt, curTick + (1 * g_eventQueue_ptr->getClock()));
+ schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
return true;
}
RubyPort::PioPort::sendTiming(PacketPtr pkt)
{
//minimum latency, must be > 0
- schedSendTiming(pkt, curTick + (1 * g_eventQueue_ptr->getClock()));
+ schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
return true;
}
// If there are still outstanding requests, keep checking
schedule(deadlockCheckEvent,
m_deadlock_threshold * g_eventQueue_ptr->getClock() +
- curTick);
+ curTick());
}
}
// See if we should schedule a deadlock check
if (deadlockCheckEvent.scheduled() == false) {
- schedule(deadlockCheckEvent, m_deadlock_threshold + curTick);
+ schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
}
Address line_addr(request->ruby_request.paddr);
//
// The main purpose for clearing stats in the unserialize process is so
// that the profiler can correctly set its start time to the unserialized
- // value of curTick
+ // value of curTick()
//
clearStats();
}
// recvAtomic() should already have turned packet into
// atomic response
assert(pkt->isResponse());
- schedSendTiming(pkt, curTick + latency);
+ schedSendTiming(pkt, curTick() + latency);
} else {
delete pkt;
}
void
SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when)
{
- assert(when > curTick);
- assert(when < curTick + SimClock::Int::ms);
+ assert(when > curTick());
+ assert(when < curTick() + SimClock::Int::ms);
// Nothing is on the list: add it and schedule an event
if (transmitList.empty() || when < transmitList.front().tick) {
if (success) {
if (!transmitList.empty() && !sendEvent->scheduled()) {
Tick time = transmitList.front().tick;
- schedule(sendEvent, time <= curTick ? curTick+1 : time);
+ schedule(sendEvent, time <= curTick() ? curTick()+1 : time);
}
if (transmitList.empty() && drainEvent && !sendEvent->scheduled()) {
/** Check whether we have a packet ready to go on the transmit list. */
bool deferredPacketReady()
- { return !transmitList.empty() && transmitList.front().tick <= curTick; }
+ { return !transmitList.empty() && transmitList.front().tick <= curTick(); }
Tick deferredPacketReadyTime()
{ return transmitList.empty() ? MaxTick : transmitList.front().tick; }
/** Attempt to send the packet at the head of the deferred packet
* list. Caller must guarantee that the deferred packet list is
- * non-empty and that the head packet is scheduled for curTick (or
+ * non-empty and that the head packet is scheduled for curTick() (or
* earlier).
*/
void sendDeferredPacket();
# Export curTick to user script.
def curTick():
- return internal.core.cvar.curTick
+ return internal.core.curTick()
# Python exit handlers happen in reverse order. We want to dump stats last.
atexit.register(internal.stats.dump)
void setClockFrequency(Tick ticksPerSecond);
-%immutable curTick;
-Tick curTick;
+Tick curTick();
class Checkpoint;
#include "base/statistics.hh"
#include "base/stats/mysql.hh"
#include "base/stats/text.hh"
+#include "sim/core.hh"
#include "sim/stat_control.hh"
%}
std::string sample);
void schedStatEvent(bool dump, bool reset,
- Tick when = curTick, Tick repeat = 0);
+ Tick when = curTick(), Tick repeat = 0);
void enable();
void prepare();
using namespace std;
-Tick curTick = 0;
+Tick _curTick = 0;
namespace SimClock {
-/// The simulated frequency of curTick. (In ticks per second)
+/// The simulated frequency of curTick(). (In ticks per second)
Tick Frequency;
namespace Float {
#include "base/types.hh"
/// The universal simulation clock.
-extern Tick curTick;
+extern Tick _curTick;
+
+inline Tick curTick() { return _curTick; }
+inline void curTick(Tick newVal) { _curTick = newVal; }
+
const Tick retryTime = 1000;
namespace SimClock {
-/// The simulated frequency of curTick.
+/// The simulated frequency of curTick().
extern Tick Frequency;
namespace Float {
EventQueue::dump() const
{
cprintf("============================================================\n");
- cprintf("EventQueue Dump (cycle %d)\n", curTick);
+ cprintf("EventQueue Dump (cycle %d)\n", curTick());
cprintf("------------------------------------------------------------\n");
if (empty())
queue = q;
#endif
#ifdef EVENTQ_DEBUG
- whenScheduled = curTick;
+ whenScheduled = curTick();
#endif
}
queue = NULL;
#endif
#ifdef EVENTQ_DEBUG
- whenCreated = curTick;
+ whenCreated = curTick();
whenScheduled = 0;
#endif
}
}
}
- // default: process all events up to 'now' (curTick)
- void serviceEvents() { serviceEvents(curTick); }
+ // default: process all events up to 'now' (curTick())
+ void serviceEvents() { serviceEvents(curTick()); }
// return true if no events are queued
bool empty() const { return head == NULL; }
void dump() const;
- Tick nextEventTime() { return empty() ? curTick : head->when(); }
+ Tick nextEventTime() { return empty() ? curTick() : head->when(); }
bool debugVerify() const;
inline void
EventQueue::schedule(Event *event, Tick when)
{
- assert((UTick)when >= (UTick)curTick);
+ assert((UTick)when >= (UTick)curTick());
assert(!event->scheduled());
assert(event->initialized());
inline void
EventQueue::reschedule(Event *event, Tick when, bool always)
{
- assert(when >= curTick);
+ assert(when >= curTick());
assert(always || event->scheduled());
assert(event->initialized());
void
abortHandler(int sigtype)
{
- ccprintf(cerr, "Program aborted at cycle %d\n", curTick);
+ ccprintf(cerr, "Program aborted at cycle %d\n", curTick());
}
/*
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
- Tick resume = curTick + SimClock::Int::ns * ns;
+ Tick resume = curTick() + SimClock::Int::ns * ns;
cpu->reschedule(quiesceEvent, resume, true);
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
- Tick resume = curTick + cpu->ticks(cycles);
+ Tick resume = curTick() + cpu->ticks(cycles);
cpu->reschedule(quiesceEvent, resume, true);
uint64_t
rpns(ThreadContext *tc)
{
- return curTick / SimClock::Int::ns;
+ return curTick() / SimClock::Int::ns;
}
void
void
m5exit(ThreadContext *tc, Tick delay)
{
- Tick when = curTick + delay * SimClock::Int::ns;
+ Tick when = curTick() + delay * SimClock::Int::ns;
exitSimLoop("m5_exit instruction encountered", 0, when);
}
return;
- Tick when = curTick + delay * SimClock::Int::ns;
+ Tick when = curTick() + delay * SimClock::Int::ns;
Tick repeat = period * SimClock::Int::ns;
Stats::schedStatEvent(false, true, when, repeat);
return;
- Tick when = curTick + delay * SimClock::Int::ns;
+ Tick when = curTick() + delay * SimClock::Int::ns;
Tick repeat = period * SimClock::Int::ns;
Stats::schedStatEvent(true, false, when, repeat);
return;
- Tick when = curTick + delay * SimClock::Int::ns;
+ Tick when = curTick() + delay * SimClock::Int::ns;
Tick repeat = period * SimClock::Int::ns;
Stats::schedStatEvent(true, true, when, repeat);
if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
return;
- Tick when = curTick + delay * SimClock::Int::ns;
+ Tick when = curTick() + delay * SimClock::Int::ns;
Tick repeat = period * SimClock::Int::ns;
exitSimLoop("checkpoint", 0, when, repeat);
Globals::serialize(ostream &os)
{
nameOut(os);
- SERIALIZE_SCALAR(curTick);
+ SERIALIZE_SCALAR(curTick());
nameOut(os, "MainEventQueue");
mainEventQueue.serialize(os);
Globals::unserialize(Checkpoint *cp)
{
const string §ion = name();
- UNSERIALIZE_SCALAR(curTick);
+ Tick tick;
+ paramIn(cp, section, "curTick", tick);
+ curTick(tick);
mainEventQueue.unserialize(cp, "MainEventQueue");
}
string
Checkpoint::setDir(const string &name)
{
- // use csprintf to insert curTick into directory name if it
+ // use csprintf to insert curTick() into directory name if it
// appears to have a format placeholder in it.
currentDirectory = (name.find("%") != string::npos) ?
- csprintf(name, curTick) : name;
+ csprintf(name, curTick()) : name;
if (currentDirectory[currentDirectory.size() - 1] != '/')
currentDirectory += "/";
return currentDirectory;
public:
// Set the current directory. This function takes care of
- // inserting curTick if there's a '%d' in the argument, and
+ // inserting curTick() if there's a '%d' in the argument, and
// appends a '/' if necessary. The final name is returned.
static std::string setDir(const std::string &base_name);
// but if you are doing this on intervals, don't forget to make another
if (repeat) {
assert(getFlags(IsMainQueue));
- mainEventQueue.schedule(this, curTick + repeat);
+ mainEventQueue.schedule(this, curTick() + repeat);
}
}
void registerExitCallback(Callback *);
/// Schedule an event to exit the simulation loop (returning to
-/// Python) at the end of the current cycle (curTick). The message
+/// Python) at the end of the current cycle (curTick()). The message
/// and exit_code parameters are saved in the SimLoopExitEvent to
/// indicate why the exit occurred.
void exitSimLoop(const std::string &message, int exit_code = 0,
- Tick when = curTick, Tick repeat = 0);
+ Tick when = curTick(), Tick repeat = 0);
#endif // __SIM_EXIT_HH__
/**
* startup() is the final initialization call before simulation.
* All state is initialized (including unserialized state, if any,
- * such as the curTick value), so this is the appropriate place to
+ * such as the curTick() value), so this is the appropriate place to
* schedule initial event(s) for objects that need them.
*/
virtual void startup();
SimLoopExitEvent *
simulate(Tick num_cycles)
{
- inform("Entering event queue @ %d. Starting simulation...\n", curTick);
+ inform("Entering event queue @ %d. Starting simulation...\n", curTick());
if (num_cycles < 0)
fatal("simulate: num_cycles must be >= 0 (was %d)\n", num_cycles);
- else if (curTick + num_cycles < 0) //Overflow
+ else if (curTick() + num_cycles < 0) //Overflow
num_cycles = MaxTick;
else
- num_cycles = curTick + num_cycles;
+ num_cycles = curTick() + num_cycles;
Event *limit_event =
new SimLoopExitEvent("simulate() limit reached", 0);
// there should always be at least one event (the SimLoopExitEvent
// we just scheduled) in the queue
assert(!mainEventQueue.empty());
- assert(curTick <= mainEventQueue.nextTick() &&
+ assert(curTick() <= mainEventQueue.nextTick() &&
"event scheduled in the past");
// forward current cycle to the time of the first event on the
// queue
- curTick = mainEventQueue.nextTick();
+ curTick(mainEventQueue.nextTick());
Event *exit_event = mainEventQueue.serviceOne();
if (exit_event != NULL) {
// hit some kind of exit event; return to Python
void process()
{
statTime.set();
- startTick = curTick;
+ startTick = curTick();
}
};
Tick
statElapsedTicks()
{
- return curTick - startTick;
+ return curTick() - startTick;
}
SimTicksReset simTicksReset;
Stats::reset();
if (repeat) {
- Stats::schedStatEvent(dump, reset, curTick + repeat, repeat);
+ Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat);
}
}
};
namespace Stats {
void initSimStats();
-void schedStatEvent(bool dump, bool reset, Tick when = curTick,
+void schedStatEvent(bool dump, bool reset, Tick when = curTick(),
Tick repeat = 0);
} // namespace Stats
#endif
DPRINTFR(SyscallVerbose,
"%d: %s: syscall %s called w/arguments %d,%d,%d,%d\n",
- curTick, tc->getCpuPtr()->name(), name,
+ curTick(), tc->getCpuPtr()->name(), name,
process->getSyscallArg(tc, index),
process->getSyscallArg(tc, index),
process->getSyscallArg(tc, index),
SyscallReturn retval = (*funcPtr)(this, callnum, process, tc);
DPRINTFR(SyscallVerbose, "%d: %s: syscall %s returns %d\n",
- curTick,tc->getCpuPtr()->name(), name, retval.value());
+ curTick(),tc->getCpuPtr()->name(), name, retval.value());
if (!(flags & SyscallDesc::SuppressReturnValue))
process->setSyscallReturn(tc, retval);
void
getElapsedTime(T1 &sec, T2 &usec)
{
- int elapsed_usecs = curTick / SimClock::Int::us;
+ int elapsed_usecs = curTick() / SimClock::Int::us;
sec = elapsed_usecs / one_million;
usec = elapsed_usecs % one_million;
}
TypedBufferArg<typename OS::tms> bufp(process->getSyscallArg(tc, index));
// Fill in the time structure (in clocks)
- int64_t clocks = curTick * OS::M5_SC_CLK_TCK / SimClock::Int::s;
+ int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / SimClock::Int::s;
bufp->tms_utime = clocks;
bufp->tms_stime = 0;
bufp->tms_cutime = 0;
s15[9].sample(1234);
s10.sample(1000000000);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s10.sample(100000);
s10.sample(100000);
s10.sample(100000);
s15[0].sample(1234);
s15[1].sample(4134);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[4].sample(1213);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[3].sample(1124);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[2].sample(1243);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[7].sample(1244);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[4].sample(7234);
s15[2].sample(9234);
s15[3].sample(1764);
s15[7].sample(1564);
s15[3].sample(3234);
s15[1].sample(2234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[5].sample(1234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[9].sample(4334);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[2].sample(1234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[4].sample(4334);
s15[6].sample(1234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[8].sample(8734);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[1].sample(5234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[3].sample(8234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[7].sample(5234);
s15[4].sample(4434);
s15[3].sample(7234);
s15[2].sample(1934);
s15[1].sample(9234);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[5].sample(5634);
s15[3].sample(1264);
s15[7].sample(5223);
s15[0].sample(1234);
s15[0].sample(5434);
s15[3].sample(8634);
- curTick += ULL(1000000);
+ curTick() += ULL(1000000);
s15[1].sample(1234);
- s4 = curTick;
+ s4 = curTick();
s8[3] = 99999;
s3 = 12;
s3++;
- curTick += 9;
+ curTick() += 9;
s1 = 9;
s1 += 9;
s9.sample(10);
s9.sample(10);
- curTick += 9;
- s4 = curTick;
+ curTick() += 9;
+ s4 = curTick();
s6.sample(100);
s6.sample(100);
s6.sample(100);
projects / gem5.git / commitdiff