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power_insn: support vec2/vec3/vec4
authorDmitry Selyutin <ghostmansd@gmail.com>
Sat, 17 Sep 2022 13:54:01 +0000 (16:54 +0300)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 16:44:16 +0000 (17:44 +0100)
src/openpower/decoder/power_insn.py patch | blob | history

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index fcb673e764c27d8d606933d5fb881ca71b317004..40b32e6d59f52e2fe20e62baba0f30732acc39f2 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1280,7 +1280,12 @@ class BaseRM(_Mapping):
 
     @property
     def specifiers(self):
-        yield from ()
+        if self.subvl == 1:
+            yield "vec2"
+        elif self.subvl == 2:
+            yield "vec3"
+        elif self.subvl == 3:
+            yield "vec4"
 
     def disassemble(self, verbosity=Verbosity.NORMAL):
         if verbosity >= Verbosity.VERBOSE: