(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index db8946cec7dcc7b61546a42488b8a25b81da0e6c..d6c1f99d928bd5a27e0e035dc2423aedebdef2c9 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -17,11 +17,16 @@ As such it brings features normally only found in Cray Supercomputers
 (Cray-1, NEC SX-Aurora)
 and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
 a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
-explicit Vector opcode exists in SV, at all**.
+explicit Vector opcode exists in SV, at all**.  It is suitable for
+low-power Embedded and DSP Workloads as much as it is for power-efficient
+Suoercomputing.
 
 Fundamental design principles:
 
-* Simplicity of introduction and implementation on the existing Power ISA
+* Taking the simplicity of the RISC paradigm and applying it strictly and
+  uniformly to create a Scalable Vector ISA.
+* Simplicity of introduction and implementation on top of
+  the existing Power ISA without disruption.
 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar
   operations
 * Preserving the underlying scalar execution dependencies as if the
@@ -31,7 +36,8 @@ Fundamental design principles:
   "context" rather than adding new instructions.
 * Does not modify or deviate from the underlying scalar Power ISA
   unless it provides significant performance or other advantage to do so
-  in the Vector space (dropping "sticky" of XER.SO for example)
+  in the Vector space (dropping the "sticky" characteristics
+  of XER.SO and CR0.SO for example)
 * Designed for Supercomputing: avoids creating significant sequential
   dependency hazards, allowing standard
   high performance superscalar multi-issue