Add "-device" argument to synth_ice40

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index abfede0111b88dd2f6bed4516df4a26870c0c683..efcea6e98fb627d17cb1965a56a2868a64544e20 100644 (file)
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,11 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))

diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/abc.box
deleted file mode 100644 (file)
index d775efa..0000000
--- a/techlibs/ice40/abc.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449

diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/abc.lut
deleted file mode 100644 (file)
index eef9978..0000000
--- a/techlibs/ice40/abc.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449

diff --git a/techlibs/ice40/hx8k.box b/techlibs/ice40/hx8k.box
new file mode 100644 (file)
index 0000000..c31f7bf
--- /dev/null
+++ b/techlibs/ice40/hx8k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316

diff --git a/techlibs/ice40/hx8k.lut b/techlibs/ice40/hx8k.lut
new file mode 100644 (file)
index 0000000..3b3bb11
--- /dev/null
+++ b/techlibs/ice40/hx8k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 91cd063a25e106b7803dd5a1b7082186aca203e5..2981875ebc4bdf316a9f28f2a211cb03a05c012c 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
                log("\n");
                log("This command runs synthesis for iCE40 FPGAs.\n");
                log("\n");
+               log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+               log("        optimise the synthesis netlist for the specified device.\n");
+               log("        HX1K is the default target if no device argument specified.\n");
+               log("\n");
                log("    -top <module>\n");
                log("        use the specified module as top module\n");
                log("\n");
@@ -102,7 +106,7 @@ struct SynthIce40Pass : public ScriptPass
        }
 
 
-       string top_opt, blif_file, edif_file, json_file, abc;
+       string top_opt, blif_file, edif_file, json_file, abc, device_opt;
        bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
        int min_ce_use;
 
@@ -124,6 +128,7 @@ struct SynthIce40Pass : public ScriptPass
                abc2 = false;
                vpr = false;
                abc = "abc";
+               device_opt = "hx1k";
        }
 
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -210,12 +215,18 @@ struct SynthIce40Pass : public ScriptPass
                                abc = "abc9";
                                continue;
                        }
+                       if (args[argidx] == "-device" && argidx+1 < args.size()) {
+                               device_opt = args[++argidx];
+                               continue;
+                       }
                        break;
                }
                extra_args(args, argidx, design);
 
                if (!design->full_selection())
                        log_cmd_error("This command only operates on fully selected designs!\n");
+               if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+                       log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
 
                log_header(design, "Executing SYNTH_ICE40 pass.\n");
                log_push();
@@ -319,7 +330,7 @@ struct SynthIce40Pass : public ScriptPass
                                if (abc == "abc9") {
                                        run("read_verilog +/ice40/abc.v");
                                        run("techmap -map +/techmap.v A:abc_box_id");
-                                       run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
+                                       run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
                                        run("blackbox A:abc_box_id");
                                }
                                else