Removed $aconst cell type

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 516a9efc3f7313b2951f09a7c26380eff5037815..569d2b6ab013ea03c18ff4c5d297f103e95dae50 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -754,7 +754,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
                break;
 
        case AST_FCALL:
-               if (str == "\\$anyconst" || str == "\\$aconst") {
+               if (str == "\\$anyconst") {
                        if (GetSize(children) == 1) {
                                while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
                                if (children[0]->type != AST_CONSTANT)
@@ -1447,9 +1447,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                } break;
 
        case AST_FCALL: {
-                       if (str == "\\$anyconst" || str == "\\$aconst")
+                       if (str == "\\$anyconst")
                        {
-                               string myid = stringf("%s$%d", RTLIL::unescape_id(str).c_str(), autoidx++);
+                               string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
                                int width = width_hint;
 
                                if (GetSize(children) > 1)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 0c46b62389269885d97b4382c0adb8f69d577527..aa2afa4ce9ac5477ce082e7308e9aeeea5e054fc 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1672,8 +1672,8 @@ skip_dynamic_range_lvalue_expansion:;
                                goto apply_newNode;
                        }
 
-                       // $anyconst and $aconst are mapped in AstNode::genRTLIL()
-                       if (str == "\\$anyconst" || str == "\\$aconst")
+                       // $anyconst is mapped in AstNode::genRTLIL()
+                       if (str == "\\$anyconst")
                                return false;
 
                        if (str == "\\$clog2")

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 28b7cd5dea550241d8693caf41f73c6ef3300f6c..c730ce5b200cb2b55c6fdbc4bebcd6ca66429653 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1229,7 +1229,7 @@ rvalue:
                $$ = new AstNode(AST_IDENTIFIER, $2);
                $$->str = *$1;
                delete $1;
-               if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$aconst"))
+               if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst"))
                        $$->type = AST_FCALL;
        } |
        hierarchical_id non_opt_multirange {

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index ebc7b3824e78c8397d626b7910e1f72b71202c14..900c12d019d85d965137728325ffe89033d233e2 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -118,7 +118,6 @@ struct CellTypes
                setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
-               setup_type("$aconst", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$equiv", {A, B}, {Y}, true);
        }
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index de492bcc625572eb08703abc510027250d0dd3c4..41b4b93f06159c0626e95c28b1df115117b3a602 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1030,7 +1030,7 @@ namespace {
                                return;
                        }
 
-                       if (cell->type.in("$aconst", "$anyconst")) {
+                       if (cell->type == "$anyconst") {
                                port("\\Y", param("\\WIDTH"));
                                check_expected();
                                return;

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index a839e0c43132367a5aa4ec44815ce216e7fe428f..bd73ae23c853b5f961b63333a309a5cd6a1fd1c8 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, and {\tt \$anyconst} cells.
 \end{fixme}
 
 \begin{fixme}

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index d0a6cd495c09047fd079a891ade5c63840f58e1d..922a47cab3ebcd5e48d7a3ba3ea0f66c148989aa 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1322,18 +1322,6 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$aconst (Y);
-
-parameter WIDTH = 0;
-
-output [WIDTH-1:0] Y;
-
-assign Y = 'bx;
-
-endmodule
-
-// --------------------------------------------------------
-
 module \$anyconst (Y);
 
 parameter WIDTH = 0;