uint32_t num_banks;
};
+struct radeon_bo_list_item {
+ struct pb_buffer *buf;
+ uint64_t vm_address;
+ uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
+};
+
struct radeon_winsys {
/**
* The screen object this winsys was created for
*/
boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
+ /**
+ * Return the buffer list.
+ *
+ * \param cs Command stream
+ * \param list Returned buffer list. Set to NULL to query the count only.
+ * \return The buffer count.
+ */
+ unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
+ struct radeon_bo_list_item *list);
+
/**
* Flush a command stream.
*
if (i >= 0) {
buffer = &cs->buffers[i];
+ buffer->priority_usage |= 1llu << priority;
buffer->usage |= usage;
*added_domains = domains & ~buffer->domains;
buffer->domains |= domains;
p_atomic_inc(&bo->num_cs_references);
buffer = &cs->buffers[cs->num_buffers];
buffer->bo = bo;
+ buffer->priority_usage = 1llu << priority;
buffer->usage = usage;
buffer->domains = domains;
return status;
}
+static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
+ struct radeon_bo_list_item *list)
+{
+ struct amdgpu_cs *cs = amdgpu_cs(rcs);
+ int i;
+
+ if (list) {
+ for (i = 0; i < cs->num_buffers; i++) {
+ pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
+ list[i].vm_address = cs->buffers[i].bo->va;
+ list[i].priority_usage = cs->buffers[i].priority_usage;
+ }
+ }
+ return cs->num_buffers;
+}
+
static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
struct pipe_fence_handle **out_fence)
{
ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
ws->base.cs_validate = amdgpu_cs_validate;
ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
+ ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
ws->base.cs_flush = amdgpu_cs_flush;
ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
ws->base.cs_sync_flush = amdgpu_cs_sync_flush;