(no commit message)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 957f9aa936b13af498d2566de7a53f4148311074..e60f6a92154f490c91174d143cf69352224cc1ca 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -113,9 +113,11 @@ bit 19=0, bit 20=0
     n3 = mask[3] & (mode[3] == creg[3])
     result = n0|n1|n2|n3 if M else n0&n1&n2&n3
     RT[63] = result # MSB0 numbering, 63 is LSB
-
+    If Rc:
+        CR0 = analyse(RT)
+ 
 When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
-SVP64 type operation and as such can use RC1 Data-dependent
+SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
 Mode capability
 
 **mfcrrweird**
@@ -133,10 +135,16 @@ bit 19=0, bit 20=0
     n3 = mask[3] & (mode[3] == creg[3])
     result = n0||n1||n2||n3
     RT[60:63] = result # MSB0 numbering, 63 is LSB
+    If Rc:
+        CR0 = analyse(RT)
 
 When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
-SVP64 type operation and as such can use RC1 Data-dependent
-Mode capability
+SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
+Mode capability.
+
+Also as noted below, element-width override bits normally used
+on the source is instead used to allow multiple results to be packed
+into the destination.  *Destination elwidth overrides still apply*
 
 **mtcrrweird**