fhdl/verilog: create clock domains in deterministic order

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 72888999c73a9a11e5ddb7e8afce777444ae164a..19bba1fa6b68f53656a22088875936630405bf03 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -323,7 +323,7 @@ def convert(f, ios=None, name="top",
     if ios is None:
         ios = set()
 
-    for cd_name in list_clock_domains(f):
+    for cd_name in sorted(list_clock_domains(f)):
         try:
             f.clock_domains[cd_name]
         except KeyError: