and raises the ideal maximum throughput to 1 instruction per clock cycle,
bearing any register hazards.
-This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/), however there's currently a
+This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/ and there are options in the Makefile to enable it), however there's currently a
task to develop the model for the simulator first. The model will be used to
determine performance.