cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses.

LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.

diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 6ed881511a67803c6aaa986da52970581f23a5d4..2ee26f2fdb7ecaa6aae401add09c06955c9eec33 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -259,24 +259,6 @@ class VexRiscvSMP(CPU):
             i_plicWishbone_DAT_MOSI  = plicbus.dat_w
         )
 
-    def set_reset_address(self, reset_address):
-        assert not hasattr(self, "reset_address")
-        self.reset_address = reset_address
-        assert reset_address == 0x00000000
-
-    def add_sources(self, platform):
-        vdir = get_data_mod("cpu", "vexriscv_smp").data_location
-        print(f"VexRiscv cluster : {self.cluster_name}")
-        if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
-            self.generate_netlist()
-
-        platform.add_source(os.path.join(vdir, "RamXilinx.v"), "verilog")
-        platform.add_source(os.path.join(vdir,  self.cluster_name + ".v"), "verilog")
-
-    def add_memory_buses(self, address_width, data_width):
-        VexRiscvSMP.litedram_width = data_width
-
-        VexRiscvSMP.generate_cluster_name()
         if VexRiscvSMP.coherent_dma:
             self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width)
             dma_bus_stall   = Signal()
@@ -301,6 +283,25 @@ class VexRiscvSMP(CPU):
                 )
             ]
 
+    def set_reset_address(self, reset_address):
+        assert not hasattr(self, "reset_address")
+        self.reset_address = reset_address
+        assert reset_address == 0x00000000
+
+    def add_sources(self, platform):
+        vdir = get_data_mod("cpu", "vexriscv_smp").data_location
+        print(f"VexRiscv cluster : {self.cluster_name}")
+        if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
+            self.generate_netlist()
+
+        platform.add_source(os.path.join(vdir, "RamXilinx.v"), "verilog")
+        platform.add_source(os.path.join(vdir,  self.cluster_name + ".v"), "verilog")
+
+    def add_memory_buses(self, address_width, data_width):
+        VexRiscvSMP.litedram_width = data_width
+
+        VexRiscvSMP.generate_cluster_name()
+
         from litedram.common import LiteDRAMNativePort
         ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)
         dbus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)