dev: Make default clock more reasonable for system and devices

This patch changes the default system clock from 1THz to 1GHz. This
clock is used by all modules that do not override the default (parent
clock), and primarily affects the IO subsystem. Every DMA device uses
its clock to schedule the next transfer, and the change will thus
cause this inter-transfer delay to be longer.

The default clock of the bus is removed, as the clock inherited from
the system provides exactly the same value.

A follow-on patch will bump the stats.

diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 447fc723e5ab16136cc692fa39b06143a2204f51..45b1f1b0a4f1d4f2225a0a90fe6e8ea0ff09d3fe 100644 (file)
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -47,8 +47,6 @@ class BaseBus(MemObject):
     abstract = True
     slave = VectorSlavePort("vector port for connecting masters")
     master = VectorMasterPort("vector port for connecting slaves")
-    # Override the default clock
-    clock = '1GHz'
     header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
     width = Param.Unsigned(8, "bus width (bytes)")
     block_size = Param.Unsigned(64, "The default block size if not set by " \

diff --git a/src/sim/System.py b/src/sim/System.py
index 88afea873831e3088bb6fcd823f31f4a1dc7dd0f..92883b299988a491969e6495d61c3f96832043ab 100644 (file)
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -42,11 +42,10 @@ class System(MemObject):
     system_port = MasterPort("System port")
 
     # Override the clock from the ClockedObject which looks at the
-    # parent clock by default
-    clock = '1t'
-    # @todo Either make this value 0 and treat it as an error if it is
-    # not overridden, or choose a more sensible value in the range of
-    # 1GHz
+    # parent clock by default. The 1 GHz default system clock serves
+    # as a start for the modules that rely on the parent to provide
+    # the clock.
+    clock = '1GHz'
 
     @classmethod
     def export_method_cxx_predecls(cls, code):