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absolute import again
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 8 Dec 2021 12:30:56 +0000 (12:30 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 8 Dec 2021 12:30:56 +0000 (12:30 +0000)
src/openpower/decoder/test/pysim.py patch | blob | history

diff --git a/src/openpower/decoder/test/pysim.py b/src/openpower/decoder/test/pysim.py
index 0d70032b29dcd0883136bc2702cf4c7d426cdc4a..531a7e836f1759e0b9737ab6f133c73a75c47154 100644 (file)
--- a/src/openpower/decoder/test/pysim.py
+++ b/src/openpower/decoder/test/pysim.py
@@ -6,7 +6,7 @@ from vcd.gtkw import GTKWSave
 from nmigen.hdl import ClockSignal, ResetSignal
 from nmigen.hdl.ast import SignalDict
 from nmigen.sim._base import BaseSignalState, BaseSimulation, BaseEngine
-from _pyrtl import _FragmentCompiler
+from openpower.decoder.test._pyrtl import _FragmentCompiler
 from nmigen.sim._pycoro import PyCoroProcess
 from nmigen.sim._pyclock import PyClockProcess