sim: support for signed numbers

diff --git a/examples/basic_sim.py b/examples/basic_sim.py
index 1786072350f3254d90d1780a59592c1324feee26..3578bc977af463a05b1fff7a7c5491b0ca5b90b6 100644 (file)
--- a/examples/basic_sim.py
+++ b/examples/basic_sim.py
@@ -5,7 +5,7 @@ from migen.sim.icarus import Runner
 class Counter:
        def __init__(self):
                self.ce = Signal()
-               self.count = Signal(BV(4))
+               self.count = Signal(BV(37, True), reset=-5)
        
        def do_simulation(self, s, cycle):
                if cycle % 2:
@@ -22,6 +22,6 @@ class Counter:
 def main():
        dut = Counter()
        sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
-       sim.run(10)
+       sim.run(20)
 
 main()

diff --git a/migen/sim/generic.py b/migen/sim/generic.py
index 79607b24fe9e2514899552594e4cf2ca0d6e42f3..60057e1ebf1d1300cc10a350811e4c5d4073d1ab 100644 (file)
--- a/migen/sim/generic.py
+++ b/migen/sim/generic.py
@@ -111,12 +111,17 @@ class Simulator:
                self.ipc.send(MessageRead(name))
                reply = self.ipc.recv()
                assert(isinstance(reply, MessageReadReply))
-               # TODO: negative numbers + cleanup LSBs
-               return reply.value
+               nbits = signal.bv.width
+               value = reply.value & (2**nbits - 1)
+               if signal.bv.signed and (value & 2**(nbits - 1)):
+                       value -= 2**nbits
+               return value
        
        def wr(self, signal, value):
                name = self.top_level.top_name + "." \
                  + self.top_level.dut_name + "." \
                  + self.namespace.get_name(signal)
-               # TODO: negative numbers
+               if value < 0:
+                       value += 2**signal.bv.width
+               assert(value >= 0 and value < 2**signal.bv.width)
                self.ipc.send(MessageWrite(name, value))