* tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,

	CpuUnknown): Renumber
	(CpuP4, CpuSSE2): New.
	(CpuUnknownFlags): Add CpuP4 and CpuSSE2

	* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
	introduced by Pentium4

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 50fd6799b31871b586ac6df23bf7fb2d38693fdc..e11c2c0194cb3df6429f7a43c1f4e581f843447b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+Wed Jan  3 16:26:52 MET 2001  Jan Hubicka  <jh@suse.cz>
+
+       * tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,
+       CpuUnknown): Renumber
+       (CpuP4, CpuSSE2): New.
+       (CpuUnknownFlags): Add CpuP4 and CpuSSE2
+
 2001-01-03  Philip Blundell  <pb@futuretv.com>
 
        * config/tc-alpha.c (alpha_force_relocation): Handle vtable

diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 964820138c01a9fbee97be0967385fb2142e0f74..0a2200b6e73ffb3b03a4fb2fda4051f196ded4f1 100644 (file)
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -279,20 +279,22 @@ typedef struct
 #define Cpu486          0x10   /* i486 or better required */
 #define Cpu586          0x20   /* i585 or better required */
 #define Cpu686          0x40   /* i686 or better required */
-#define CpuK6           0x80   /* AMD K6 or better required*/
-#define CpuAthlon      0x100   /* AMD Athlon or better required*/
-#define CpuSledgehammer 0x200  /* Sledgehammer or better required */
-#define CpuMMX         0x400   /* MMX support required */
-#define CpuSSE         0x800   /* Streaming SIMD extensions required */
-#define Cpu3dnow       0x1000  /* 3dnow! support required */
-#define CpuUnknown     0x2000  /* The CPU is unknown,  be on the safe side.  */
+#define CpuP4           0x80   /* Pentium4 or better required */
+#define CpuK6          0x100   /* AMD K6 or better required*/
+#define CpuAthlon      0x200   /* AMD Athlon or better required*/
+#define CpuSledgehammer 0x400  /* Sledgehammer or better required */
+#define CpuMMX         0x800   /* MMX support required */
+#define CpuSSE        0x1000   /* Streaming SIMD extensions required */
+#define CpuSSE2               0x2000   /* Streaming SIMD extensions 2 required */
+#define Cpu3dnow       0x4000  /* 3dnow! support required */
+#define CpuUnknown     0x8000  /* The CPU is unknown,  be on the safe side.  */
 
   /* These flags are set by gas depending on the flag_code.  */
 #define Cpu64       0x4000000   /* 64bit support required  */
 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 
   /* The default value for unknown CPUs - enable all features to avoid problems.  */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSledgehammer|CpuMMX|CpuSSE|Cpu3dnow|CpuK6|CpuAthlon)
+#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
 
   /* the bits in opcode_modifier are used to generate the final opcode from
      the base_opcode.  These bits also are used to detect alternate forms of

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 5e0b3ec295be358929ffa68bbdfb138d27da7dce..ccb5dd1cb9f3bfb4c2ab10241da1127aa8df9523 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+Wed Jan  3 16:27:15 MET 2001  Jan hubicka  <jh@suse.cz>
+
+       * i386.h (i386_optab): Fix 64bit pushf template; Add instructions
+       introduced by Pentium4
+
 Sat Dec 30 19:03:15 MET 2000  Jan hubicka  <jh@suse.cz>
 
        * i386.h (i386_optab): Add "rex*" instructions;

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index c2b1dd6682e038283e3543a8a59d624e2929dcf1..17400ea9a9163932d9fe86ddcf6f9ebf9c4b7d26 100644 (file)
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -208,8 +208,10 @@ static const template i386_optab[] = {
 {"cmc",           0,   0xf5, X, 0,      NoSuf,                 { 0, 0, 0} },
 {"lahf",   0,  0x9f, X, CpuNo64,NoSuf,                 { 0, 0, 0} },
 {"sahf",   0,  0x9e, X, CpuNo64,NoSuf,                 { 0, 0, 0} },
-{"pushf",  0,  0x9c, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
-{"popf",   0,  0x9d, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
+{"pushf",  0,  0x9c, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
+{"pushf",  0,  0x9c, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"popf",   0,  0x9d, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
+{"popf",   0,  0x9d, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"stc",           0,   0xf9, X, 0,      NoSuf,                 { 0, 0, 0} },
 {"std",           0,   0xfd, X, 0,      NoSuf,                 { 0, 0, 0} },
 {"sti",           0,   0xfb, X, 0,      NoSuf,                 { 0, 0, 0} },
@@ -947,14 +949,26 @@ static const template i386_optab[] = {
 {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm,                { 0, 0, 0} },
 {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm,                { FloatReg, 0, 0} },
 
-/* MMX instructions.  */
+/* Pentium4 extensions.  */
+
+{"movnti",    2, 0x0fc3,    X, CpuP4, lq_Suf|Modrm,    { WordReg|WordMem, WordReg, 0 } },
+{"clflush",   1, 0x0fae,    7, CpuP4, FP|Modrm,        { ByteMem, 0, 0 } },
+{"lfence",    0, 0x0faee8,  X, CpuP4, FP,              { 0, 0, 0 } },
+{"mfence",    0, 0x0faef0,  X, CpuP4, FP,              { 0, 0, 0 } },
+{"pause",     0, 0xf390,    X, CpuP4, FP,              { 0, 0, 0 } },
+
+/* MMX/SSE2 instructions.  */
 
 {"emms",     0, 0x0f77, X, CpuMMX, FP,                 { 0, 0, 0 } },
 {"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,           { Reg32|LongMem, RegMMX, 0 } },
 {"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,           { RegMMX, Reg32|LongMem, 0 } },
+{"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,           { Reg32|LLongMem, RegXMM, 0 } },
+{"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,           { RegXMM, Reg32|LLongMem, 0 } },
 /* Real MMX instructions.  */
 {"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
 {"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,           { RegMMX, RegMMX|LongMem, 0 } },
+{"movq",     2, 0xf30f7e,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
+{"movq",     2, 0x660fd6,X,CpuSSE2,FP|Modrm,           { RegXMM, RegXMM|LLongMem, 0 } },
 /* In the 64bit mode the short form mov immediate is redefined to have
    64bit displacement value.  */
 {"movq",   2,  0x88, X, Cpu64,  NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
@@ -965,58 +979,109 @@ static const template i386_optab[] = {
 {"movq",   2, 0x0f20, X, Cpu64,         NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
 {"movq",   2, 0x0f21, X, Cpu64,         NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
 {"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddb",    2, 0x0ffc, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddb",    2, 0x660ffc,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddw",    2, 0x0ffd, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddw",    2, 0x660ffd,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddd",    2, 0x0ffe, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddd",    2, 0x660ffe,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddsb",   2, 0x0fec, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddsb",   2, 0x660fec,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddsw",   2, 0x0fed, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddsw",   2, 0x660fed,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddusb",  2, 0x0fdc, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddusb",  2, 0x660fdc,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddusw",  2, 0x0fdd, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"paddusw",  2, 0x660fdd,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pand",     2, 0x0fdb, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pand",     2, 0x660fdb,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pandn",    2, 0x0fdf, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pandn",    2, 0x660fdf,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pcmpeqb",  2, 0x0f74, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqb",  2, 0x660f74,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pcmpeqw",  2, 0x0f75, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqw",  2, 0x660f75,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pcmpeqd",  2, 0x0f76, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqd",  2, 0x660f76,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pcmpgtb",  2, 0x0f64, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtb",  2, 0x660f64,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pcmpgtw",  2, 0x0f65, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtw",  2, 0x660f65,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pcmpgtd",  2, 0x0f66, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtd",  2, 0x660f66,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pmaddwd",  2, 0x0ff5, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pmaddwd",  2, 0x660ff5,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pmulhw",   2, 0x0fe5, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhw",   2, 0x660fe5,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pmullw",   2, 0x0fd5, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pmullw",   2, 0x660fd5,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"por",             2, 0x0feb, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
+{"por",             2, 0x660feb,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
 {"psllw",    2, 0x0ff1, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psllw",    2, 0x660ff1,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psllw",    2, 0x0f71, 6, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psllw",    2, 0x660f71,6,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"pslld",    2, 0x0ff2, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"pslld",    2, 0x660ff2,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pslld",    2, 0x0f72, 6, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"pslld",    2, 0x660f72,6,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psllq",    2, 0x0ff3, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psllq",    2, 0x660ff3,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psllq",    2, 0x0f73, 6, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psllq",    2, 0x660f73,6,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psraw",    2, 0x0fe1, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psraw",    2, 0x660fe1,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psraw",    2, 0x0f71, 4, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psraw",    2, 0x660f71,4,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psrad",    2, 0x0fe2, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psrad",    2, 0x660fe2,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psrad",    2, 0x0f72, 4, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psrad",    2, 0x660f72,4,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psrlw",    2, 0x0fd1, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psrlw",    2, 0x660fd1,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psrlw",    2, 0x0f71, 2, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psrlw",    2, 0x660f71,2,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psrld",    2, 0x0fd2, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psrld",    2, 0x660fd2,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psrld",    2, 0x0f72, 2, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psrld",    2, 0x660f72,2,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psrlq",    2, 0x0fd3, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psrlq",    2, 0x660fd3,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psrlq",    2, 0x0f73, 2, CpuMMX, FP|Modrm,           { Imm8, RegMMX, 0 } },
+{"psrlq",    2, 0x660f73,2,CpuSSE2,FP|Modrm,           { Imm8, RegXMM, 0 } },
 {"psubb",    2, 0x0ff8, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubb",    2, 0x660ff8,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubw",    2, 0x0ff9, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubw",    2, 0x660ff9,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubd",    2, 0x0ffa, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubd",    2, 0x660ffa,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubsb",   2, 0x0fe8, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubsb",   2, 0x660fe8,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubsw",   2, 0x0fe9, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubsw",   2, 0x660fe9,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubusb",  2, 0x0fd8, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubusb",  2, 0x660fd8,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubusw",  2, 0x0fd9, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"psubusw",  2, 0x660fd9,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"pxor",     2, 0x0fef, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
-
+{"pxor",     2, 0x660fef,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 
 /* PIII Katmai New Instructions / SIMD instructions.  */
 
@@ -1068,6 +1133,7 @@ static const template i386_optab[] = {
 {"movmskps",  2, 0x0f50,    X, CpuSSE, FP|Modrm,       { RegXMM|InvMem, Reg32, 0 } },
 {"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm,       { RegXMM, LLongMem, 0 } },
 {"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm,       { RegMMX, LLongMem, 0 } },
+{"movntq",    2, 0x660fe7,  X, CpuSSE2,FP|Modrm,       { RegXMM, LLongMem, 0 } },
 {"movss",     2, 0xf30f10,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"movss",     2, 0xf30f11,  X, CpuSSE, FP|Modrm,       { RegXMM, RegXMM|WordMem, 0 } },
 {"movups",    2, 0x0f10,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1076,21 +1142,32 @@ static const template i386_optab[] = {
 {"mulss",     2, 0xf30f59,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"orps",      2, 0x0f56,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pavgb",     2, 0x0fe0,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgb",     2, 0x660fe0,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgw",     2, 0x660fe3,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pextrw",    3, 0x0fc5,    X, CpuSSE, FP|Modrm,       { Imm8, RegMMX, Reg32|InvMem } },
+{"pextrw",    3, 0x660fc5,  X, CpuSSE2,FP|Modrm,       { Imm8, RegXMM, Reg32|InvMem } },
 {"pinsrw",    3, 0x0fc4,    X, CpuSSE, FP|Modrm,       { Imm8, Reg32|ShortMem, RegMMX } },
 {"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxsw",    2, 0x660fee,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pmaxub",    2, 0x0fde,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxub",    2, 0x660fde,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pminsw",    2, 0x0fea,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pminsw",    2, 0x660fea,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pminub",    2, 0x660fda,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pmovmskb",  2, 0x0fd7,    X, CpuSSE, FP|Modrm,       { RegMMX, Reg32|InvMem, 0 } },
+{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,FP|Modrm,       { RegXMM, Reg32|InvMem, 0 } },
 {"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"prefetchnta", 1, 0x0f18,  0, CpuSSE, FP|Modrm,       { LLongMem, 0, 0 } },
 {"prefetcht0",  1, 0x0f18,  1, CpuSSE, FP|Modrm,       { LLongMem, 0, 0 } },
 {"prefetcht1",  1, 0x0f18,  2, CpuSSE, FP|Modrm,       { LLongMem, 0, 0 } },
 {"prefetcht2",  1, 0x0f18,  3, CpuSSE, FP|Modrm,       { LLongMem, 0, 0 } },
 {"psadbw",    2, 0x0ff6,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
+{"psadbw",    2, 0x660ff6,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pshufw",    3, 0x0f70,    X, CpuSSE, FP|Modrm,       { Imm8, RegMMX|LLongMem, RegMMX } },
+{"pshufw",    3, 0x660f70,  X, CpuSSE2,FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
 {"rcpps",     2, 0x0f53,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"rcpss",     2, 0xf30f53,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"rsqrtps",   2, 0x0f52,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1107,6 +1184,93 @@ static const template i386_optab[] = {
 {"unpcklps",  2, 0x0f14,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"xorps",     2, 0x0f57,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 
+/* SSE-2 instructions.  */
+
+{"addpd",     2, 0x660f58,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"addsd",     2, 0xf20f58,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"andnpd",    2, 0x660f55,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"andpd",     2, 0x660f54,  X, CpuSSE2, FP|Modrm,      { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmplepd",   2, 0x660fc2,  2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmppd",     3, 0x660fc2,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
+{"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LongMem, RegXMM } },
+{"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,      { RegMMX|LLongMem, RegXMM, 0 } },
+{"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, FP|Modrm,      { Reg32|LongMem, RegXMM, 0 } },
+{"divpd",     2, 0x660f5e,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"divsd",     2, 0xf20f5e,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"maxpd",     2, 0x660f5f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"maxsd",     2, 0xf20f5f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"minpd",     2, 0x660f5d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"minsd",     2, 0xf20f5d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"movapd",    2, 0x660f28,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"movapd",    2, 0x660f29,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LLongMem, 0 } },
+{"movhpd",    2, 0x660f16,  X, CpuSSE2, FP|Modrm,      { LLongMem, RegXMM, 0 } },
+{"movhpd",    2, 0x660f17,  X, CpuSSE2, FP|Modrm,      { RegXMM, LLongMem, 0 } },
+{"movlpd",    2, 0x660f12,  X, CpuSSE2, FP|Modrm,      { LLongMem, RegXMM, 0 } },
+{"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,      { RegXMM, LLongMem, 0 } },
+{"movmskpd",  2, 0x660f50,  X, CpuSSE2, FP|Modrm,      { RegXMM|InvMem, Reg32, 0 } },
+{"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm,      { RegXMM, LLongMem, 0 } },
+{"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LongMem, 0 } },
+{"movupd",    2, 0x660f10,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"movupd",    2, 0x660f11,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LLongMem, 0 } },
+{"mulpd",     2, 0x660f59,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"mulsd",     2, 0xf20f59,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"orpd",      2, 0x660f56,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"shufpd",    3, 0x660fc6,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtpd",    2, 0x660f51,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"subpd",     2, 0x660f5c,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"subsd",     2, 0xf20f5c,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"ucomisd",   2, 0x660f2e,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"unpckhpd",  2, 0x660f15,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklpd",  2, 0x660f14,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"xorpd",     2, 0x660f57,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, Reg32, 0 } },
+{"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, FP|Modrm,      { RegXMM|WordMem, Reg32, 0 } },
+{"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM, 0 } },
+{"movdqa",    2, 0x660f6f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"movdqa",    2, 0x660f7f,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LLongMem, 0 } },
+{"movdqu",    2, 0xf30f6f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"movdqu",    2, 0xf30f7f,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LLongMem, 0 } },
+{"movq2q",    2, 0xf20fd6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"pmuludq",   2, 0x0ff4,    X, CpuSSE2, FP|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
+{"pmuludq",   2, 0x660ff4,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
+{"pshufd",    3, 0x660f70,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pshufhw",   3, 0xf30f70,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pshuflw",   3, 0xf20f70,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pslldq",    2, 0x660f73,  7, CpuSSE2, FP|Modrm,      { Imm8, RegXMM, 0 } },
+{"psrldq",    2, 0x660f73,  3, CpuSSE2, FP|Modrm,      { Imm8, RegXMM, 0 } },
+{"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+
 /* AMD 3DNow! instructions.  */
 
 {"prefetch", 1, 0x0f0d,           0, Cpu3dnow, FP|Modrm,               { ByteMem, 0, 0 } },