Parse macro call attached semicolon as empty expression

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 18745e38eece4d90c33bb51df9cec62079c85386..35e34a124f0dd95551bbb52d493de60d5b80e0bd 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -745,7 +745,7 @@ module_body:
 module_body_stmt:
        task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
        enum_decl | struct_decl |
-       always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
+       always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
 
 checker_decl:
        TOK_CHECKER TOK_ID ';' {