add fault-first link to ARM SVE2

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 6f4e1e1794263c6a242205867ec903a7b9771178..16f0edfd62e7a385c76d3dbdbc31fc84cba3f6ca 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -11,7 +11,7 @@
 * {3}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files
 * {4}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit.
 * {5}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations
-* {6} See [[sv/svp64/appendix]]
+* {6} See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
 * {7} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
 * {8} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
 * {9} VSX's Vector Registers are mis-named: they are PackedSIMD.