add ternary operator sel ? a : b

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 9ef2cb324f14f07ffc0717cee1239d89bce1ecea..e02866c372ea506e72fd23533f777bf6c551a816 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -94,6 +94,9 @@ class _Operator(Value):
                self.op = op
                self.operands = operands
 
+def Mux(sel, val1, val0):
+       return _Operator("m", [sel, val1, val0])
+
 class _Slice(Value):
        def __init__(self, value, start, stop):
                Value.__init__(self)

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index fa6ce3cfa01a593191b41e56d769f8a311d7cd1b..10bd7e37290a06c7508d0dad48097d47981a495f 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -58,6 +58,16 @@ def _printexpr(ns, node):
                                        r2 = "$signed({1'd0, " + r2 + "})"
                        r = r1 + " " + node.op + " " + r2
                        s = s1 or s2
+               elif arity == 3:
+                       assert node.op == "m"
+                       r2, s2 = _printexpr(ns, node.operands[1])
+                       r3, s3 = _printexpr(ns, node.operands[2])
+                       if s2 and not s3:
+                               r3 = "$signed({1'd0, " + r3 + "})"
+                       if s3 and not s2:
+                               r2 = "$signed({1'd0, " + r2 + "})"
+                       r = r1 + " ? " + r2 + " : " + r3
+                       s = s2 or s3
                else:
                        raise TypeError
                return "(" + r + ")", s