fhdl/verilog: tristate outputs are always wire

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index bc0a19c44ad018679700a90f96173b4239572722..c5ba2272a0bae12a96734ca2f8b709c6883f6fdb 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -135,10 +135,10 @@ def _list_comb_wires(f):
 
 def _printheader(f, ios, name, ns):
        sigs = list_signals(f) | list_special_ios(f, True, True, True)
-       it_mem_outs = list_special_ios(f, False, True, False)
+       special_outs = list_special_ios(f, False, True, True)
        inouts = list_special_ios(f, False, False, True)
-       targets = list_targets(f) | it_mem_outs
-       wires = _list_comb_wires(f) | it_mem_outs
+       targets = list_targets(f) | special_outs
+       wires = _list_comb_wires(f) | special_outs
        r = "module " + name + "(\n"
        firstp = True
        for sig in sorted(ios, key=lambda x: x.huid):