Rename {A,B} -> {A2,B2}

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index df3d60e09e01dcc4f979ccc9cd89d6d5da8f1e05..52ffa54653a33dc67b52472a1b4e43a0f7cdcfea 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -258,8 +258,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
        log("\n");
        log("preAdd:     %s\n", log_id(st.preAdd, "--"));
        log("ffAD:       %s %s %s\n", log_id(st.ffAD, "--"), log_id(st.ffADcemux, "--"), log_id(st.ffADrstmux, "--"));
-       log("ffA:        %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
-       log("ffB:        %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
+       log("ffA2:       %s %s %s\n", log_id(st.ffA2, "--"), log_id(st.ffA2cemux, "--"), log_id(st.ffA2rstmux, "--"));
+       log("ffB2:       %s %s %s\n", log_id(st.ffB2, "--"), log_id(st.ffB2cemux, "--"), log_id(st.ffB2rstmux, "--"));
        log("ffC:        %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--"));
        log("ffD:        %s %s %s\n", log_id(st.ffD, "--"), log_id(st.ffDcemux, "--"), log_id(st.ffDrstmux, "--"));
        log("dsp:        %s\n", log_id(st.dsp, "--"));
@@ -367,16 +367,16 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                        }
                };
 
-               if (st.ffA) {
-                       SigSpec &A = cell->connections_.at("\\A");
-                       f(A, st.ffA, st.ffAcemux, st.ffAcepol, "\\CEA2", st.ffArstmux, st.ffArstpol, "\\RSTA");
-                       pm.add_siguser(A, cell);
+               if (st.ffA2) {
+                       SigSpec &A2 = cell->connections_.at("\\A");
+                       f(A2, st.ffA2, st.ffA2cemux, st.ffA2cepol, "\\CEA2", st.ffA2rstmux, st.ffArstpol, "\\RSTA");
+                       pm.add_siguser(A2, cell);
                        cell->setParam("\\AREG", 1);
                }
-               if (st.ffB) {
-                       SigSpec &B = cell->connections_.at("\\B");
-                       f(B, st.ffB, st.ffBcemux, st.ffBcepol, "\\CEB2", st.ffBrstmux, st.ffBrstpol, "\\RSTB");
-                       pm.add_siguser(B, cell);
+               if (st.ffB2) {
+                       SigSpec &B2 = cell->connections_.at("\\B");
+                       f(B2, st.ffB2, st.ffB2cemux, st.ffB2cepol, "\\CEB2", st.ffB2rstmux, st.ffBrstpol, "\\RSTB");
+                       pm.add_siguser(B2, cell);
                        cell->setParam("\\BREG", 1);
                }
                if (st.ffC) {
@@ -406,14 +406,14 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 
                log("  clock: %s (%s)", log_signal(st.clock), "posedge");
 
-               if (st.ffA)
-                       log(" ffA:%s", log_id(st.ffA));
+               if (st.ffA2)
+                       log(" ffA2:%s", log_id(st.ffA2));
 
                if (st.ffAD)
                        log(" ffAD:%s", log_id(st.ffAD));
 
-               if (st.ffB)
-                       log(" ffB:%s", log_id(st.ffB));
+               if (st.ffB2)
+                       log(" ffB2:%s", log_id(st.ffB2));
 
                if (st.ffC)
                        log(" ffC:%s", log_id(st.ffC));

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 6998d6e844313c91c1308b1a5fc794e893fdf54e..8c7477efad88f4e3ff988f660e9b73ff2c7058e0 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -4,10 +4,11 @@ udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigBit> clock
 state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
 state <IdString> postAddAB postAddMuxAB
-state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol
+state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol
 state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol
 
-state <Cell*> ffAD ffADcemux ffADrstmux ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffC ffCcemux ffCrstmux
+state <Cell*> ffAD ffADcemux ffADrstmux ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
+state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux ffC ffCcemux ffCrstmux
 state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
 
 // subpattern
@@ -103,20 +104,20 @@ code sigA sigD
        }
 endcode
 
-code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol
-       // Only search for ffA if there was a pre-adder
-       //   (otherwise ffA would have been matched as ffAD)
+code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol
+       // Only search for ffA2 if there was a pre-adder
+       //   (otherwise ffA2 would have been matched as ffA2)
        if (preAdd) {
                if (param(dsp, \AREG).as_int() == 0) {
                        argQ = sigA;
                        subpattern(in_dffe);
                        if (dff) {
-                               ffA = dff;
+                               ffA2 = dff;
                                clock = dffclock;
                                if (dffcemux) {
-                                       ffAcemux = dffcemux;
-                                       ffArstmux = dffrstmux;
-                                       ffAcepol = dffcepol;
+                                       ffA2cemux = dffcemux;
+                                       ffA2rstmux = dffrstmux;
+                                       ffA2cepol = dffcepol;
                                        ffArstpol = dffrstpol;
                                }
                                sigA = dffD;
@@ -126,26 +127,26 @@ code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock ffAD ffADcemux ff
        // And if there wasn't a pre-adder,
        //   move AD register to A
        else if (ffAD) {
-               log_assert(!ffA && !ffAcemux && !ffArstmux);
-               std::swap(ffA, ffAD);
-               std::swap(ffAcemux, ffADcemux);
-               std::swap(ffArstmux, ffADrstmux);
-               ffAcepol = ffADcepol;
+               log_assert(!ffA2 && !ffA2cemux && !ffA2rstmux);
+               std::swap(ffA2, ffAD);
+               std::swap(ffA2cemux, ffADcemux);
+               std::swap(ffA2rstmux, ffADrstmux);
+               ffA2cepol = ffADcepol;
                ffArstpol = ffADrstpol;
        }
 endcode
 
-code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock
+code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock
        if (param(dsp, \BREG).as_int() == 0) {
                argQ = sigB;
                subpattern(in_dffe);
                if (dff) {
-                       ffB = dff;
+                       ffB2 = dff;
                        clock = dffclock;
                        if (dffcemux) {
-                               ffBcemux = dffcemux;
-                               ffBrstmux = dffrstmux;
-                               ffBcepol = dffcepol;
+                               ffB2cemux = dffcemux;
+                               ffB2rstmux = dffrstmux;
+                               ffB2cepol = dffcepol;
                                ffBrstpol = dffrstpol;
                        }
                        sigB = dffD;