class L1Cache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 20
is_top_level = True
class L2Cache(BaseCache):
assoc = 8
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 20
tgts_per_mshr = 12
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# Instruction Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7a_ICache(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 2
tgts_per_mshr = 8
# Data Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7a_DCache(BaseCache):
- latency = '2ns'
+ hit_latency = '2ns'
+ response_latency = '2ns'
block_size = 64
mshrs = 6
tgts_per_mshr = 8
# TLB Cache
# Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(BaseCache):
- latency = '4ns'
+ hit_latency = '4ns'
+ response_latency = '4ns'
block_size = 64
mshrs = 6
tgts_per_mshr = 8
# L2 Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
class O3_ARM_v7aL2(BaseCache):
- latency = '12ns'
+ hit_latency = '12ns'
+ response_latency = '12ns'
block_size = 64
mshrs = 16
tgts_per_mshr = 8
type = 'BaseCache'
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- latency = Param.Latency("Latency")
+ hit_latency = Param.Latency("The hit latency for this cache")
+ response_latency = Param.Latency(
+ "Additional cache latency for the return path to core on a miss");
hash_delay = Param.Cycles(1, "time in cycles of hash access")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
MSHRQueue_WriteBuffer),
blkSize(p->block_size),
- hitLatency(p->latency),
+ hitLatency(p->hit_latency),
+ responseLatency(p->response_latency),
numTarget(p->tgts_per_mshr),
forwardSnoops(p->forward_snoops),
isTopLevel(p->is_top_level),
/**
* The latency of a hit in this device.
*/
- int hitLatency;
+ const Tick hitLatency;
+
+ /**
+ * The latency of sending reponse to its upper level cache/core on a
+ * linefill. In most contemporary processors, the return path on a cache
+ * miss is much quicker that the hit latency. The responseLatency parameter
+ * tries to capture this latency.
+ */
+ const Tick responseLatency;
/** The number of targets for each MSHR. */
const int numTarget;
#if defined(USE_CACHE_FALRU)
#define BUILD_FALRU_CACHE do { \
- FALRU *tags = new FALRU(block_size, size, latency); \
+ FALRU *tags = new FALRU(block_size, size, hit_latency); \
BUILD_CACHE(FALRU, tags); \
} while (0)
#else
#if defined(USE_CACHE_LRU)
#define BUILD_LRU_CACHE do { \
- LRU *tags = new LRU(numSets, block_size, assoc, latency); \
+ LRU *tags = new LRU(numSets, block_size, assoc, hit_latency); \
BUILD_CACHE(LRU, tags); \
} while (0)
#else
iic_params.blkSize = block_size;
iic_params.assoc = assoc;
iic_params.hashDelay = hash_delay;
- iic_params.hitLatency = latency;
+ iic_params.hitLatency = hit_latency;
iic_params.rp = repl;
iic_params.subblockSize = subblock_size;
#else
transfer_offset += blkSize;
}
- // If critical word (no offset) return first word time
- completion_time = tags->getHitLatency() +
+ // If critical word (no offset) return first word time.
+ // responseLatency is the latency of the return path
+ // from lower level caches/memory to an upper level cache or
+ // the core.
+ completion_time = responseLatency +
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
assert(!target->pkt->req->isUncacheable());
assert(target->pkt->cmd == MemCmd::StoreCondReq ||
target->pkt->cmd == MemCmd::StoreCondFailReq ||
target->pkt->cmd == MemCmd::SCUpgradeFailReq);
- completion_time = tags->getHitLatency() + pkt->finishTime;
+ // responseLatency is the latency of the return path
+ // from lower level caches/memory to an upper level cache or
+ // the core.
+ completion_time = responseLatency + pkt->finishTime;
target->pkt->req->setExtraData(0);
} else {
// not a cache fill, just forwarding response
- completion_time = tags->getHitLatency() + pkt->finishTime;
+ // responseLatency is the latency of the return path
+ // from lower level cahces/memory to the core.
+ completion_time = responseLatency + pkt->finishTime;
if (pkt->isRead() && !is_error) {
target->pkt->setData(pkt->getPtr<uint8_t>());
}
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
cpu = InOrderCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', latency='10ns'))
+ MyCache(size = '2MB', hit_latency='10ns',
+ response_latency='10ns'))
cpu.clock = '2GHz'
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 12
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', latency='10ns'))
+ MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns'))
system = System(cpu = cpu,
physmem = SimpleMemory(),
membus = CoherentBus())
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
projects / gem5.git / commitdiff