boards/plarforms/minispartan6: default to xc6slx25

diff --git a/litex/boards/platforms/minispartan6.py b/litex/boards/platforms/minispartan6.py
index e0fc4af2cc574e8e6a6a0e83d29b477cbae07bb5..c32b72eeed3ce36755c0185090bff1e739ed0b7b 100644 (file)
--- a/litex/boards/platforms/minispartan6.py
+++ b/litex/boards/platforms/minispartan6.py
@@ -117,7 +117,7 @@ class Platform(XilinxPlatform):
     default_clk_name = "clk32"
     default_clk_period = 31.25
 
-    def __init__(self, device="xc6slx9"):
+    def __init__(self, device="xc6slx25"):
         XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
 
     def create_programmer(self):