(no commit message)

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 359d3e454b818ae26f928ed5de965c3141dd2308..d7f98720cbbe23001f2498191b72fcf89cb7babe 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -118,7 +118,7 @@ It leaves space for future expansion to RV128 and/or multi-register predicates.
 
 GETVL add1 SETVL is a pain. 3 operations because VL is a CSR it is not possible to perform arithmetic on it.
 
-What about actually marking one of the registers *as* VL?
+What about actually marking one of the registers *as* VL?  this would save a *lot* of instructions.
 
 ----
 
@@ -127,3 +127,4 @@ Setting VL from an immed without altering MVL is not possible in the above pseud
 # links
 
 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001881.html>
+* <https://groups.google.com/d/msg/comp.arch/MLfqE8Rm-X4/zHLCHg6UAQAJ>