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-# SV (Simple Vectorisation) for the Power ISA
+# SV (Simple Scalar Vectorisation) for the Power ISA
**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
for-loop had been expanded as actual scalar instructions
(termed "preserving Program Order")
* Augments ("tags") existing instructions, providing Vectorisation
- "context" rather than adding new ones.
+ "context" rather than adding new instructions.
* Does not modify or deviate from the underlying scalar Power ISA
unless it provides significant performance or other advantage to do so
- in the Vector space (dropping XER.SO for example)
+ in the Vector space (dropping "sticky" of XER.SO for example)
* Designed for Supercomputing: avoids creating significant sequential
- dependency hazards, allowing high performance superscalar
- microarchitectures to be deployed.
+ dependency hazards, allowing standard
+ high performance superscalar multi-issue
+ micro-architectures to be leveraged.
Advantages of these design principles: